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Fix Verilog module typo. Adjust RBL route.

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mrg
2021-05-06 14:32:47 -07:00
parent c057490923
commit e995e61ea4
2 changed files with 8 additions and 4 deletions
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compiler/modules/delay_chain.py
+8 -3
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@@ -191,13 +191,18 @@ class delay_chain(design.design):
def add_layout_pins(self):
# input is A pin of first inverter
# It gets routed to the left a bit to prevent pin access errors
# due to the output pin when going up to M3
a_pin = self.driver_inst_list[0].get_pin("A")
mid_loc = vector(a_pin.cx() - self.m3_pitch, a_pin.cy())
self.add_via_stack_center(from_layer=a_pin.layer,
to_layer="m2",
offset=a_pin.center())
to_layer="m2",
offset=mid_loc)
self.add_path(a_pin.layer, [a_pin.center(), mid_loc])
self.add_layout_pin_rect_center(text="in",
layer="m2",
offset=a_pin.center())
offset=mid_loc)
# output is A pin of last load/fanout inverter
last_driver_inst = self.driver_inst_list[-1]