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Fix Verilog module typo. Adjust RBL route.

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mrg
2021-05-06 14:32:47 -07:00
parent c057490923
commit e995e61ea4
2 changed files with 8 additions and 4 deletions
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compiler/base/verilog.py
-1
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@@ -70,7 +70,6 @@ class verilog:
self.vf.write(" parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n")
self.vf.write("\n")
self.vf.write("module {0}(\n".format(self.name))
self.vf.write("`ifdef USE_POWER_PINS\n")
self.vf.write(" inout vdd;\n")
self.vf.write(" inout gnd;\n")