Change some debug levels. Fix ngspice test values. ix cwd warning in some tests.

compiler/calibre.py

@@ -90,6 +90,7 @@ def run_drc(name, gds_name):
     f.close()
 
     # run drc
+    cwd = os.getcwd()
     os.chdir(OPTS.openram_temp)
     errfile = "%s%s.drc.err" % (OPTS.openram_temp, name)
     outfile = "%s%s.drc.out" % (OPTS.openram_temp, name)
@@ -98,6 +99,7 @@ def run_drc(name, gds_name):
         OPTS.calibre_exe, OPTS.openram_temp, errfile, outfile)
     debug.info(1, cmd)
     os.system(cmd)
+    os.chdir(cwd)
 
     # check the result for these lines in the summary:
     # TOTAL Original Layer Geometries: 106 (157)
@@ -163,6 +165,7 @@ def run_lvs(name, gds_name, sp_name):
     f.close()
 
     # run LVS
+    cwd = os.getcwd()
     os.chdir(OPTS.openram_temp)
     errfile = "%s%s.lvs.err" % (OPTS.openram_temp, name)
     outfile = "%s%s.lvs.out" % (OPTS.openram_temp, name)
@@ -171,6 +174,7 @@ def run_lvs(name, gds_name, sp_name):
         OPTS.openram_temp, errfile, outfile)
     debug.info(2, cmd)
     os.system(cmd)
+    os.chdir(cwd)
 
     # check the result for these lines in the summary:
     f = open(lvs_runset['lvsReportFile'], "r")
@@ -265,6 +269,7 @@ def run_pex(name, gds_name, sp_name, output=None):
     f.close()
 
     # run pex
+    cwd = os.getcwd()
     os.chdir(OPTS.openram_temp)
     errfile = "{0}{1}.pex.err".format(OPTS.openram_temp, name)
     outfile = "{0}{1}.pex.out".format(OPTS.openram_temp, name)
@@ -275,6 +280,7 @@ def run_pex(name, gds_name, sp_name, output=None):
                                                                     outfile)
     debug.info(2, cmd)
     os.system(cmd)
+    os.chdir(cwd)
 
     # also check the output file
     f = open(outfile, "r")

compiler/contact.py

@@ -18,7 +18,7 @@ class contact(design.design):
                                            dimensions[1],
                                            contact.unique_contact_id)
         design.design.__init__(self, name)
-        debug.info(2, "create contact object {0}".format(name))
+        debug.info(3, "create contact object {0}".format(name))
         contact.unique_contact_id += 1
 
         self.layer_stack = layer_stack

compiler/globals.py

@@ -140,7 +140,6 @@ def end_openram():
     
 def cleanup_paths():
     # we should clean up this temp directory after execution...
-
     if os.path.exists(OPTS.openram_temp):
         shutil.rmtree(OPTS.openram_temp, ignore_errors=True)
             
@@ -161,7 +160,7 @@ def setup_paths():
 
     if not OPTS.openram_temp.endswith('/'):
         OPTS.openram_temp += "/"
-    debug.info(1, "Temporary files saved in " + OPTS.openram_temp)
+    debug.info(0, "Temporary files saved in " + OPTS.openram_temp)
 
     cleanup_paths()
 

compiler/hierarchy_layout.py

@@ -245,14 +245,14 @@ class layout:
            Otherwise, start a new layout for dynamic generation."""
         # open the gds file if it exists or else create a blank layout
         if os.path.isfile(self.gds_file):
-            debug.info(2, "opening %s" % self.gds_file)
+            debug.info(3, "opening %s" % self.gds_file)
             self.gds = gdsMill.VlsiLayout(units=GDS["unit"])
             reader = gdsMill.Gds2reader(self.gds)
             reader.loadFromFile(self.gds_file)
             # TODO: parse the width/height
             # TODO: parse the pin locations
         else:
-            debug.info(2, "creating structure %s" % self.name)
+            debug.info(3, "creating structure %s" % self.name)
             self.gds = gdsMill.VlsiLayout(
                 name=self.name, units=GDS["unit"])
 

compiler/hierarchy_spice.py

@@ -68,7 +68,7 @@ class spice:
         """Reads the sp file (and parse the pins) from the library 
            Otherwise, initialize it to null for dynamic generation"""
         if os.path.isfile(self.sp_file):
-            debug.info(2, "opening {0}".format(self.sp_file))
+            debug.info(3, "opening {0}".format(self.sp_file))
             f = open(self.sp_file)
             self.spice = f.readlines()
             for i in range(len(self.spice)):

compiler/options.py

@@ -6,6 +6,7 @@ class options(optparse.Values):
     """
     Class for holding all of the OpenRAM options.
     """
+
     # This is the technology directory.
     openram_tech = ""
     # This is the name of the technology.

compiler/path.py

@@ -20,7 +20,7 @@ class path(design.design):
         name = "path_{0}".format(path.unique_path_id)
         path.unique_path_id += 1
         design.design.__init__(self, name)
-        debug.info(2, "create path obj {0}".format(name))
+        debug.info(3, "create path obj {0}".format(name))
 
         self.name = name
         self.layer_name = layer

compiler/ptx.py

@@ -16,7 +16,7 @@ class ptx(design.design):
         name = "{0}{1}".format(name, ptx.unique_mos_id)
         ptx.unique_mos_id += 1
         design.design.__init__(self, name)
-        debug.info(2, "create ptx structure {0}".format(name))
+        debug.info(3, "create ptx structure {0}".format(name))
 
         self.tx_type = tx_type
         self.mults = mults

compiler/tests/21_ngspice_delay_test.py

@@ -47,12 +47,11 @@ class timing_sram_test(unittest.TestCase):
         d = delay.delay(s,tempspice)
         data = d.analyze(probe_address, probe_data)
 
-        print data
         if OPTS.tech_name == "freepdk45":
-            self.assertTrue(isclose(data['delay1'],0.013649))
+            self.assertTrue(isclose(data['delay1'],0.01333683)) # diff than hspice
-            self.assertTrue(isclose(data['delay0'],0.22893))
+            self.assertTrue(isclose(data['delay0'],0.23396480000000003)) # diff than hspice
-            self.assertTrue(isclose(data['min_period1'],0.078582763671875))
+            self.assertTrue(isclose(data['min_period1'],0.079193115234375)) # diff than hspice
-            self.assertTrue(isclose(data['min_period0'],0.25543212890625))
+            self.assertTrue(isclose(data['min_period0'],0.260162353515625)) # diff than hspice
         elif OPTS.tech_name == "scn3me_subm":
             self.assertTrue(isclose(data['delay1'],1.617351)) # diff than hspice
             self.assertTrue(isclose(data['delay0'],0.2980481)) # diff than hspice

compiler/tests/regress.py

@@ -9,8 +9,8 @@ import globals
 (OPTS, args) = globals.parse_args()
 del sys.argv[1:]
 
-import header
+from testutils import header
-header.header(__file__, OPTS.tech_name)
+header(__file__, OPTS.tech_name)
 
 # get a list of all files in the tests directory
 files = os.listdir(sys.path[0])

compiler/wire.py

@@ -20,7 +20,7 @@ class wire(path):
         name = "wire_{0}".format(wire.unique_wire_id)
         wire.unique_wire_id += 1
         design.design.__init__(self, name)
-        debug.info(2, "create wire obj {0}".format(name))
+        debug.info(3, "create wire obj {0}".format(name))
 
         self.layer_stack = layer_stack
         self.position_list = position_list