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Update to space according to the bitcell array.
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@@ -68,17 +68,10 @@ class write_driver_array(design.design):
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def create_layout(self):
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if self.bitcell.width > self.driver.width:
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self.width = (self.columns + self.num_spare_cols) * self.bitcell.width
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self.width_regular_cols = self.columns * self.bitcell.width
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self.single_col_width = self.bitcell.width
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else:
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self.width = (self.columns + self.num_spare_cols) * self.driver.width
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self.width_regular_cols = self.columns * self.driver.width
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self.single_col_width = self.driver.width
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self.height = self.driver.height
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self.place_write_array()
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self.width = self.driver_insts[-1].rx()
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self.width_regular_cols = self.driver_insts[-self.num_spare_cols].rx()
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self.height = self.driver.height
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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@@ -109,14 +102,14 @@ class write_driver_array(design.design):
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self.bitcell = factory.create(module_type="bitcell")
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def create_write_array(self):
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self.driver_insts = {}
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self.driver_insts = []
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w = 0
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windex=0
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for i in range(0, self.columns, self.words_per_row):
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name = "write_driver{}".format(i)
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index = int(i / self.words_per_row)
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self.driver_insts[index]=self.add_inst(name=name,
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mod=self.driver)
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self.driver_insts.append(self.add_inst(name=name,
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mod=self.driver))
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if self.write_size:
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self.connect_inst([self.data_name + "_{0}".format(index),
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@@ -148,8 +141,8 @@ class write_driver_array(design.design):
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else:
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offset = 1
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name = "write_driver{}".format(self.columns + i)
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self.driver_insts[index]=self.add_inst(name=name,
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mod=self.driver)
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self.driver_insts.append(self.add_inst(name=name,
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mod=self.driver))
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self.connect_inst([self.data_name + "_{0}".format(index),
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self.get_bl_name() + "_{0}".format(index),
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@@ -178,7 +171,6 @@ class write_driver_array(design.design):
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self.driver_insts[i].place(offset=base, mirror=mirror)
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# place spare write drivers (if spare columns are specified)
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for i, xoffset in enumerate(self.offsets[self.columns:]):
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index = self.word_size + i
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