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Update to space according to the bitcell array.

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This commit is contained in:
mrg
2020-09-14 12:05:45 -07:00
parent 4482c63d6f
commit e95ab66916
10 changed files with 74 additions and 69 deletions
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compiler/modules/sense_amp_array.py
+23 -21
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@@ -6,12 +6,11 @@
# All rights reserved.
#
import design
from tech import drc
from vector import vector
from sram_factory import factory
import debug
from globals import OPTS
import logical_effort
from tech import cell_properties
class sense_amp_array(design.design):
@@ -29,6 +28,7 @@ class sense_amp_array(design.design):
self.word_size = word_size
self.words_per_row = words_per_row
self.columns = word_size * words_per_row
self.offsets = offsets
if not num_spare_cols:
self.num_spare_cols = 0
@@ -69,16 +69,15 @@ class sense_amp_array(design.design):
self.create_sense_amp_array()
def create_layout(self):
self.height = self.amp.height
if self.bitcell.width > self.amp.width:
self.width = self.bitcell.width * (self.word_size * self.words_per_row + self.num_spare_cols)
else:
self.width = self.amp.width * (self.word_size * self.words_per_row + self.num_spare_cols)
self.place_sense_amp_array()
self.height = self.amp.height
self.width = self.local_insts[-1].rx()
self.add_layout_pins()
self.route_rails()
self.add_boundary()
self.DRC_LVS()
@@ -112,29 +111,32 @@ class sense_amp_array(design.design):
self.en_name, "vdd", "gnd"])
def place_sense_amp_array(self):
from tech import cell_properties
if self.bitcell.width > self.amp.width:
self.amp_spacing = self.bitcell.width
else:
self.amp_spacing = self.amp.width
if not self.offsets:
self.offsets = []
for i in range(self.num_cols + self.num_spare_cols):
self.offsets.append(i * self.bitcell.width)
for i in range(0, self.row_size, self.words_per_row):
index = int(i / self.words_per_row)
xoffset = i * self.bitcell.width
if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
for i, xoffset in enumerate(self.offsets[0:self.columns:self.words_per_row]):
if cell_properties.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2:
mirror = "MY"
xoffset = xoffset + self.amp.width
xoffset = xoffset + self.amp_spacing
else:
mirror = ""
amp_position = vector(xoffset, 0)
self.local_insts[index].place(offset=amp_position, mirror=mirror)
self.local_insts[i].place(offset=amp_position, mirror=mirror)
# place spare sense amps (will share the same enable as regular sense amps)
for i in range(0, self.num_spare_cols):
for i, xoffset in enumerate(self.offsets[self.columns:]):
index = self.word_size + i
xoffset = ((self.word_size * self.words_per_row) + i) * self.bitcell.width
if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
if cell_properties.bitcell.mirror.y and (index + self.column_offset) % 2:
mirror = "MY"
xoffset = xoffset + self.amp.width
xoffset = xoffset + self.amp_width
else:
mirror = ""