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Fix missing attributes

This commit is contained in:
mrg 2020-11-13 19:04:26 -08:00
parent b4342ac527
commit e9420d57c2
2 changed files with 3 additions and 2 deletions
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2
compiler/bitcells/replica_bitcell_2port.py
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@ -42,7 +42,7 @@ class replica_bitcell_2port(bitcell_base.bitcell_base):
"""Adds edges to graph. Multiport bitcell timing graph is too complex """Adds edges to graph. Multiport bitcell timing graph is too complex
to use the add_graph_edges function.""" to use the add_graph_edges function."""
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)} pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
pins = props.bitcell.cell_2port.pin pins = props.bitcell_2port.pin
# Edges hardcoded here. Essentially wl->bl/br for both ports. # Edges hardcoded here. Essentially wl->bl/br for both ports.
# Port 0 edges # Port 0 edges
graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self) graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)

3
compiler/modules/dff_array.py
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@ -7,6 +7,7 @@
# #
import debug import debug
import design import design
from tech import custom_properties as props
from vector import vector from vector import vector
from sram_factory import factory from sram_factory import factory
from globals import OPTS from globals import OPTS
@ -137,7 +138,7 @@ class dff_array(design.design):
height=dout_pin.height()) height=dout_pin.height())
# Create vertical spines to a single horizontal rail # Create vertical spines to a single horizontal rail
clk_pin = self.dff_insts[0, 0].get_pin(self.dff.clk_pin) clk_pin = self.dff_insts[0, 0].get_pin(props.dff.pin.clk)
clk_ypos = 2 * self.m3_pitch + self.m3_width clk_ypos = 2 * self.m3_pitch + self.m3_width
debug.check(clk_pin.layer == "m2", "DFF clk pin not on metal2") debug.check(clk_pin.layer == "m2", "DFF clk pin not on metal2")
self.add_layout_pin_segment_center(text="clk", self.add_layout_pin_segment_center(text="clk",