Separate get_ and get_all for bitlines and wordlines

compiler/modules/replica_bitcell_array.py

@@ -471,12 +471,41 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
             return self.rbl_bitline_names[port]
 
     def get_bitline_names(self, port=None):
-        """ Return the BL for the given RBL port """
+        """ Return the regular bitlines for the given port or all"""
         if port == None:
             return self.all_bitline_names
         else:
             return self.bitline_names[port]
         
+    def get_all_bitline_names(self):
+        """ Return ALL the bitline names (including dummy and rbl) """
+        temp = []
+        temp.extend(self.get_dummy_bitline_names(0))
+        temp.extend(self.get_rbl_bitline_names(0))
+        temp.extend(self.get_bitline_names())
+        if len(self.all_ports) > 1:
+            temp.extend(self.get_rbl_bitline_names(1))
+        temp.extend(self.get_dummy_bitline_names(1))
+        return temp
+
+    def get_wordline_names(self, port=None):
+        """ Return the regular wordline names """
+        if port == None:
+            return self.all_wordline_names
+        else:
+            return self.wordline_names[port]
+    
+    def get_all_wordline_names(self):
+        """ Return all the wordline names """
+        temp = []
+        temp.extend(self.get_dummy_wordline_names(0))
+        temp.extend(self.get_rbl_wordline_names(0))
+        temp.extend(self.all_wordline_names)
+        if len(self.all_ports) > 1:
+            temp.extend(self.rbl_wordline_names(1))
+        temp.extend(self.get_dummy_wordline_names(1))
+        return temp
+        
     def get_dummy_wordline_names(self, port=None):
         """ 
         Return the ACTIVE WL for the given dummy port.