luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 01:48:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

Separate get_ and get_all for bitlines and wordlines

Browse Source
This commit is contained in:
mrg
2020-08-25 17:08:48 -07:00
parent bdb18b4cab
commit e92337ddaf
4 changed files with 34 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/local_bitcell_array.py
+1 -1
View File
@@ -104,7 +104,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
# Connect unused RBL WL to gnd
array_rbl_names = set([x for x in self.bitcell_array.get_all_wordline_names() if x.startswith("rbl")])
dummy_rbl_names = set([x for x in self.bitcell_array.get_all_wordline_names() if x.startswith("dummy")])
rbl_wl_names = set([self.bitcell_array.get_rbl_wordline_names(x) for x in self.all_ports])
rbl_wl_names = set([x for port in self.all_ports for x in self.bitcell_array.get_rbl_wordline_names(port)])
self.gnd_wl_names = list((array_rbl_names - rbl_wl_names) | dummy_rbl_names)
self.all_array_wordline_inputs = [x + "i" if x not in self.gnd_wl_names else "gnd" for x in self.bitcell_array.get_wordline_names()]