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Merge branch 'dev' into multiport_characterization

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This commit is contained in:
Hunter Nichols
2018-11-19 15:42:48 -08:00
parent a55d907d03 b13d938ea8
commit e8f1c19af6
30 changed files with 783 additions and 930 deletions
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compiler/modules/bank.py
+12 -8
View File
@@ -61,7 +61,8 @@ class bank(design.design):
#self.add_lvs_correspondence_points()
# Remember the bank center for further placement
self.bank_center=self.offset_all_coordinates().scale(-1,-1)
self.bank_array_ll = self.offset_all_coordinates().scale(-1,-1)
self.bank_array_ur = self.bitcell_array_inst.ur()
self.DRC_LVS()
@@ -232,8 +233,8 @@ class bank(design.design):
self.row_decoder_offsets[port] = vector(-x_offset,0)
# LOWER LEFT QUADRANT
# Place the col decoder right aligned with row decoder (x_offset doesn't change)
# Below the bitcell array
# Place the col decoder left aligned with row decoder (x_offset doesn't change)
# Below the bitcell array with well spacing
if self.col_addr_size > 0:
y_offset = self.column_decoder.height
else:
@@ -290,8 +291,11 @@ class bank(design.design):
# UPPER RIGHT QUADRANT
# Place the col decoder right aligned with row decoder (x_offset doesn't change)
# Below the bitcell array
y_offset = self.bitcell_array.height + self.m2_gap
# Above the bitcell array with a well spacing
if self.col_addr_size > 0:
y_offset = self.bitcell_array.height + self.column_decoder.height
else:
y_offset = self.bitcell_array.height
y_offset += 2*drc("well_to_well")
self.column_decoder_offsets[port] = vector(x_offset,y_offset)
@@ -723,7 +727,7 @@ class bank(design.design):
for port in self.all_ports:
if port%2 == 1:
mirror = "MY"
mirror = "XY"
else:
mirror = "R0"
self.column_decoder_inst[port].place(offset=offsets[port], mirror=mirror)
@@ -1189,8 +1193,8 @@ class bank(design.design):
# clk to wordline_driver
control_signal = self.prefix+"clk_buf{}".format(port)
pin_pos = self.wordline_driver_inst[port].get_pin("en").uc()
mid_pos = pin_pos + vector(0,self.m1_pitch)
pin_pos = self.wordline_driver_inst[port].get_pin("en").bc()
mid_pos = pin_pos - vector(0,self.m1_pitch)
control_x_offset = self.bus_xoffset[port][control_signal].x
control_pos = vector(control_x_offset, mid_pos.y)
self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos])
compiler/modules/bitcell_array.py
+7 -2
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@@ -4,7 +4,7 @@ from tech import drc, spice
from vector import vector
from globals import OPTS
unique_id = 1
class bitcell_array(design.design):
"""
@@ -12,8 +12,13 @@ class bitcell_array(design.design):
and word line is connected by abutment.
Connects the word lines and bit lines.
"""
unique_id = 1
def __init__(self, cols, rows, name=""):
def __init__(self, cols, rows, name="bitcell_array"):
if name == "":
name = "bitcell_array_{0}x{1}_{2}".format(rows,cols,bitcell_array.unique_id)
bitcell_array.unique_id += 1
design.design.__init__(self, name)
debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
compiler/modules/dff_buf.py
+4 -2
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@@ -12,11 +12,13 @@ class dff_buf(design.design):
with two inverters, of variable size, to provide q
and qbar. This is to enable driving large fanout loads.
"""
unique_id = 1
def __init__(self, inv1_size=2, inv2_size=4, name=""):
if name=="":
name = "dff_buf_{0}_{1}".format(inv1_size, inv2_size)
name = "dff_buf_{0}".format(dff_buf.unique_id)
dff_buf.unique_id += 1
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
compiler/modules/dff_buf_array.py
+4 -2
View File
@@ -11,13 +11,15 @@ class dff_buf_array(design.design):
This is a simple row (or multiple rows) of flops.
Unlike the data flops, these are never spaced out.
"""
unique_id = 1
def __init__(self, rows, columns, inv1_size=2, inv2_size=4, name=""):
self.rows = rows
self.columns = columns
if name=="":
name = "dff_buf_array_{0}x{1}".format(rows, columns)
name = "dff_buf_array_{0}x{1}_{2}".format(rows, columns, dff_buf_array.unique_id)
dff_buf_array.unique_id += 1
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
self.inv1_size = inv1_size
compiler/modules/dff_inv.py
+4 -2
View File
@@ -11,11 +11,13 @@ class dff_inv(design.design):
This is a simple DFF with an inverted output. Some DFFs
do not have Qbar, so this will create it.
"""
unique_id = 1
def __init__(self, inv_size=2, name=""):
if name=="":
name = "dff_inv_{0}".format(inv_size)
name = "dff_inv_{0}".format(dff_inv.unique_id)
dff_inv.unique_id += 1
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
self.inv_size = inv_size
compiler/modules/dff_inv_array.py
+4 -2
View File
@@ -11,13 +11,15 @@ class dff_inv_array(design.design):
This is a simple row (or multiple rows) of flops.
Unlike the data flops, these are never spaced out.
"""
unique_id = 1
def __init__(self, rows, columns, inv_size=2, name=""):
self.rows = rows
self.columns = columns
if name=="":
name = "dff_inv_array_{0}x{1}".format(rows, columns)
name = "dff_inv_array_{0}x{1}_{2}".format(rows, columns, dff_inv_array.unique_id)
dff_inv_array.unique_id += 1
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
self.inv_size = inv_size
compiler/modules/replica_bitline.py
+1 -1
View File
@@ -89,7 +89,7 @@ class replica_bitline(design.design):
self.add_mod(self.bitcell)
# This is the replica bitline load column that is the height of our array
self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.bitcell_loads)
self.rbl = bitcell_array(cols=1, rows=self.bitcell_loads)
self.add_mod(self.rbl)
# FIXME: The FO and depth of this should be tuned