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Change wen to en in spice lib files. Check lvs report insted of stdout with netgen.

This commit is contained in:
Matt Guthaus 2018-02-01 05:38:48 -08:00 committed by Hunter Nichols
parent e4295ea61b
commit e8d001a3f9
3 changed files with 18 additions and 20 deletions
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16
compiler/verify/magic.py
View File

@ -193,6 +193,7 @@ def run_lvs(cell_name, gds_name, sp_name):
os.chdir(OPTS.openram_temp) os.chdir(OPTS.openram_temp)
errfile = "{0}{1}.lvs.err".format(OPTS.openram_temp, cell_name) errfile = "{0}{1}.lvs.err".format(OPTS.openram_temp, cell_name)
outfile = "{0}{1}.lvs.out".format(OPTS.openram_temp, cell_name) outfile = "{0}{1}.lvs.out".format(OPTS.openram_temp, cell_name)
resultsfile = "{0}lvs.results".format(OPTS.openram_temp, cell_name)
cmd = "{0}run_lvs.sh lvs 2> {1} 1> {2}".format(OPTS.openram_temp, cmd = "{0}run_lvs.sh lvs 2> {1} 1> {2}".format(OPTS.openram_temp,
errfile, errfile,
@ -202,7 +203,7 @@ def run_lvs(cell_name, gds_name, sp_name):
os.chdir(cwd) os.chdir(cwd)
# check the result for these lines in the summary: # check the result for these lines in the summary:
f = open(outfile, "r") f = open(resultsfile, "r")
results = f.readlines() results = f.readlines()
f.close() f.close()
@ -213,8 +214,12 @@ def run_lvs(cell_name, gds_name, sp_name):
# There were property errors. # There were property errors.
test = re.compile("Property errors were found.") test = re.compile("Property errors were found.")
propertyerrors = filter(test.search, results) propertyerrors = filter(test.search, results)
# Require pins to match?
# Cell pin lists for pnand2_1.spice and pnand2_1 altered to match.
test = re.compile(".*altered to match.")
pinerrors = filter(test.search, results)
total_errors = len(propertyerrors) + len(incorrect) total_errors = len(propertyerrors) + len(incorrect) + len(pinerrors)
# If we want to ignore property errors # If we want to ignore property errors
#total_errors = len(incorrect) #total_errors = len(incorrect)
#if len(propertyerrors)>0: #if len(propertyerrors)>0:
@ -227,14 +232,7 @@ def run_lvs(cell_name, gds_name, sp_name):
if correct == 0: if correct == 0:
total_errors += 1 total_errors += 1
# Require pins to match?
# Cell pin lists for pnand2_1.spice and pnand2_1 altered to match.
if total_errors>0: if total_errors>0:
# check the result for these lines in the summary:
f = open("{}lvs.results".format(OPTS.openram_temp), "r")
results = f.readlines()
f.close()
# Just print out the whole file, it is short. # Just print out the whole file, it is short.
for e in results: for e in results:
debug.info(1,e.strip("\n")) debug.info(1,e.strip("\n"))

12
technology/freepdk45/sp_lib/write_driver.sp
View File

@ -3,19 +3,19 @@
*inverters for enable and data input *inverters for enable and data input
minP bl_bar din vdd vdd pmos_vtg w=360.000000n l=50.000000n minP bl_bar din vdd vdd pmos_vtg w=360.000000n l=50.000000n
minN bl_bar din gnd gnd nmos_vtg w=180.000000n l=50.000000n minN bl_bar din gnd gnd nmos_vtg w=180.000000n l=50.000000n
moutP wen_bar wen vdd vdd pmos_vtg w=360.000000n l=50.000000n moutP en_bar en vdd vdd pmos_vtg w=360.000000n l=50.000000n
moutN wen_bar wen gnd gnd nmos_vtg w=180.000000n l=50.000000n moutN en_bar en gnd gnd nmos_vtg w=180.000000n l=50.000000n
*tristate for BL *tristate for BL
mout0P int1 bl_bar vdd vdd pmos_vtg w=360.000000n l=50.000000n mout0P int1 bl_bar vdd vdd pmos_vtg w=360.000000n l=50.000000n
mout0P2 bl wen_bar int1 vdd pmos_vtg w=360.000000n l=50.000000n mout0P2 bl en_bar int1 vdd pmos_vtg w=360.000000n l=50.000000n
mout0N bl wen int2 gnd nmos_vtg w=180.000000n l=50.000000n mout0N bl en int2 gnd nmos_vtg w=180.000000n l=50.000000n
mout0N2 int2 bl_bar gnd gnd nmos_vtg w=180.000000n l=50.000000n mout0N2 int2 bl_bar gnd gnd nmos_vtg w=180.000000n l=50.000000n
*tristate for BR *tristate for BR
mout1P int3 din vdd vdd pmos_vtg w=360.000000n l=50.000000n mout1P int3 din vdd vdd pmos_vtg w=360.000000n l=50.000000n
mout1P2 br wen_bar int3 vdd pmos_vtg w=360.000000n l=50.000000n mout1P2 br en_bar int3 vdd pmos_vtg w=360.000000n l=50.000000n
mout1N br wen int4 gnd nmos_vtg w=180.000000n l=50.000000n mout1N br en int4 gnd nmos_vtg w=180.000000n l=50.000000n
mout1N2 int4 din gnd gnd nmos_vtg w=180.000000n l=50.000000n mout1N2 int4 din gnd gnd nmos_vtg w=180.000000n l=50.000000n
.ENDS write_driver .ENDS write_driver

10
technology/scn3me_subm/sp_lib/write_driver.sp
View File

@ -6,9 +6,9 @@ M_1 net_3 din gnd gnd n W='1.2*1u' L=0.6u
M_2 net_3 din vdd vdd p W='2.1*1u' L=0.6u M_2 net_3 din vdd vdd p W='2.1*1u' L=0.6u
**** 2input nand gate follwed by inverter to drive BL ****** **** 2input nand gate follwed by inverter to drive BL ******
M_3 net_2 wen net_7 gnd n W='2.1*1u' L=0.6u M_3 net_2 en net_7 gnd n W='2.1*1u' L=0.6u
M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u
M_5 net_2 wen vdd vdd p W='2.1*1u' L=0.6u M_5 net_2 en vdd vdd p W='2.1*1u' L=0.6u
M_6 net_2 din vdd vdd p W='2.1*1u' L=0.6u M_6 net_2 din vdd vdd p W='2.1*1u' L=0.6u
@ -17,8 +17,8 @@ M_8 net_1 net_2 gnd gnd n W='1.2*1u' L=0.6u
**** 2input nand gate follwed by inverter to drive BR****** **** 2input nand gate follwed by inverter to drive BR******
M_9 net_4 wen vdd vdd p W='2.1*1u' L=0.6u M_9 net_4 en vdd vdd p W='2.1*1u' L=0.6u
M_10 net_4 wen net_8 gnd n W='2.1*1u' L=0.6u M_10 net_4 en net_8 gnd n W='2.1*1u' L=0.6u
M_11 net_8 net_3 gnd gnd n W='2.1*1u' L=0.6u M_11 net_8 net_3 gnd gnd n W='2.1*1u' L=0.6u
M_12 net_4 net_3 vdd vdd p W='2.1*1u' L=0.6u M_12 net_4 net_3 vdd vdd p W='2.1*1u' L=0.6u
@ -29,7 +29,7 @@ M_14 net_6 net_4 gnd gnd n W='1.2*1u' L=0.6u
M_15 bl net_6 net_5 gnd n W='3.6*1u' L=0.6u M_15 bl net_6 net_5 gnd n W='3.6*1u' L=0.6u
M_16 br net_1 net_5 gnd n W='3.6*1u' L=0.6u M_16 br net_1 net_5 gnd n W='3.6*1u' L=0.6u
M_17 net_5 wen gnd gnd n W='3.6*1u' L=0.6u M_17 net_5 en gnd gnd n W='3.6*1u' L=0.6u