mirror of https://github.com/VLSIDA/OpenRAM.git
Skip psram 1 bank
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@ -11,7 +11,7 @@ import globals
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from globals import OPTS
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from globals import OPTS
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import debug
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import debug
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#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
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@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
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class sram_1bank_test(openram_test):
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class sram_1bank_test(openram_test):
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def runTest(self):
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def runTest(self):
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