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Fixed conflict in delay.py

This commit is contained in:
Hunter Nichols 2018-02-27 13:02:22 -08:00
parent d0e6dc9ce7 01244347c1
commit e6d6680da1
185 changed files with 4308533 additions and 915 deletions
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1
.gitattributes vendored Normal file
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@ -0,0 +1 @@
*.sp linguist-vendored

1
.gitignore vendored
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@ -1,7 +1,6 @@
.DS_Store .DS_Store
*~ *~
*.pyc *.pyc
*.log
*.aux *.aux
*.out *.out
*.toc *.toc

11
CONTRIBUTING.md
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@ -96,15 +96,14 @@ the tests on your contributions before they will be accepted.
git pull upstream dev git pull upstream dev
``` ```
9. Merge the changes from dev into your branch 9. Frequently rebase your branch to keep track of current changes in dev.
``` ```
git merge dev git fetch upstream
git rebase origin/dev
``` ```
10. After you are done, rebase your branch to minimize the number of commits if you
had a lot. I prefer a single commit that you contribute. After this, 10. After a final rebase and your code is working, push your branch to YOUR repository:
push your branch to YOUR repository:
``` ```
git rebase dev
git push -u origin useful-branch-name git push -u origin useful-branch-name
``` ```
Remember origin is your copy on github and useful-branch-name is the Remember origin is your copy on github and useful-branch-name is the

2
compiler/characterizer/charutils.py
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@ -27,7 +27,7 @@ def parse_output(filename, key):
if val != None: if val != None:
debug.info(4, "Key = " + key + " Val = " + val.group(1)) debug.info(4, "Key = " + key + " Val = " + val.group(1))
return val.group(1) return convert_to_float(val.group(1))
else: else:
return "Failed" return "Failed"

676
compiler/characterizer/delay.py
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@ -1,34 +1,54 @@
import sys import sys,re,shutil
import re
import debug import debug
import tech import tech
import math import math
import stimuli import stimuli
from trim_spice import trim_spice
import charutils as ch import charutils as ch
import utils import utils
from globals import OPTS from globals import OPTS
class delay(): class delay():
""" """Functions to measure the delay and power of an SRAM at a given address and
Functions to measure the delay of an SRAM at a given address and
data bit. data bit.
In general, this will perform the following actions:
1) Trim the netlist to remove unnecessary logic.
2) Find a feasible clock period using max load/slew on the trimmed netlist.
3) Characterize all loads/slews and consider fail when delay is greater than 5% of feasible delay using trimmed netlist.
4) Measure the leakage during the last cycle of the trimmed netlist when there is no operation.
5) Measure the leakage of the whole netlist (untrimmed) in each corner.
6) Subtract the trimmed leakage and add the untrimmed leakage to the power.
Netlist trimming can be removed by setting OPTS.trim_netlist to
False, but this is VERY slow.
""" """
def __init__(self,sram,spfile, corner): def __init__(self, sram, spfile, corner):
self.sram = sram
self.name = sram.name self.name = sram.name
self.num_words = sram.num_words self.word_size = self.sram.word_size
self.word_size = sram.word_size self.addr_size = self.sram.addr_size
self.addr_size = sram.addr_size self.num_cols = self.sram.num_cols
self.sram_sp_file = spfile self.num_rows = self.sram.num_rows
self.num_banks = self.sram.num_banks
self.sp_file = spfile
# These are the member variables for a simulation
self.period = 0
self.set_load_slew(0,0)
self.set_corner(corner) self.set_corner(corner)
def set_corner(self,corner): def set_corner(self,corner):
""" Set the corner values """ """ Set the corner values """
self.corner = corner self.corner = corner
(self.process, self.vdd_voltage, self.temperature) = corner (self.process, self.vdd_voltage, self.temperature) = corner
self.gnd_voltage = 0
def set_load_slew(self,load,slew):
""" Set the load and slew """
self.load = load
self.slew = slew
def check_arguments(self): def check_arguments(self):
"""Checks if arguments given for write_stimulus() meets requirements""" """Checks if arguments given for write_stimulus() meets requirements"""
@ -43,27 +63,10 @@ class delay():
if not isinstance(self.probe_data, int) or self.probe_data>self.word_size or self.probe_data<0: if not isinstance(self.probe_data, int) or self.probe_data>self.word_size or self.probe_data<0:
debug.error("Given probe_data is not an integer to specify a data bit",1) debug.error("Given probe_data is not an integer to specify a data bit",1)
def write_generic_stimulus(self):
def write_stimulus(self, period, load, slew): """ Create the instance, supplies, loads, and access transistors. """
""" Creates a stimulus file for simulations to probe a bitcell at a given clock period.
Address and bit were previously set with set_probe().
Input slew (in ns) and output capacitive load (in fF) are required for charaterization.
"""
self.check_arguments()
# obtains list of time-points for each rising clk edge
self.obtain_cycle_times(period)
# creates and opens stimulus file for writing
temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
self.sf = open(temp_stim, "w")
self.sf.write("* Stimulus for period of {0}n load={1}fF slew={2}ns\n\n".format(period,load,slew))
self.stim = stimuli.stimuli(self.sf, self.corner)
# include files in stimulus file
self.stim.write_include(self.sram_sp_file)
# add vdd/gnd statements # add vdd/gnd statements
self.sf.write("\n* Global Power Supplies\n") self.sf.write("\n* Global Power Supplies\n")
self.stim.write_supply() self.stim.write_supply()
@ -75,52 +78,123 @@ class delay():
self.sf.write("\n* SRAM output loads\n") self.sf.write("\n* SRAM output loads\n")
for i in range(self.word_size): for i in range(self.word_size):
self.sf.write("CD{0} d[{0}] 0 {1}f\n".format(i,load)) self.sf.write("CD{0} d[{0}] 0 {1}f\n".format(i,self.load))
# add access transistors for data-bus # add access transistors for data-bus
self.sf.write("\n* Transmission Gates for data-bus and control signals\n") self.sf.write("\n* Transmission Gates for data-bus and control signals\n")
self.stim.inst_accesstx(dbits=self.word_size) self.stim.inst_accesstx(dbits=self.word_size)
def write_delay_stimulus(self):
""" Creates a stimulus file for simulations to probe a bitcell at a given clock period.
Address and bit were previously set with set_probe().
Input slew (in ns) and output capacitive load (in fF) are required for charaterization.
"""
self.check_arguments()
# obtains list of time-points for each rising clk edge
self.obtain_cycle_times()
# creates and opens stimulus file for writing
temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
self.sf = open(temp_stim, "w")
self.sf.write("* Delay stimulus for period of {0}n load={1}fF slew={2}ns\n\n".format(self.period,
self.load,
self.slew))
self.stim = stimuli.stimuli(self.sf, self.corner)
# include files in stimulus file
self.stim.write_include(self.trim_sp_file)
self.write_generic_stimulus()
# generate data and addr signals # generate data and addr signals
self.sf.write("\n* Generation of data and address signals\n") self.sf.write("\n* Generation of data and address signals\n")
for i in range(self.word_size): for i in range(self.word_size):
if i == self.probe_data: if i == self.probe_data:
self.gen_data(clk_times=self.cycle_times, self.gen_data(clk_times=self.cycle_times,
sig_name="data[{0}]".format(i), sig_name="data[{0}]".format(i))
period=period,
slew=slew)
else: else:
self.stim.gen_constant(sig_name="d[{0}]".format(i), self.stim.gen_constant(sig_name="d[{0}]".format(i),
v_val=self.gnd_voltage) v_val=0)
self.gen_addr(clk_times=self.cycle_times, self.gen_addr(clk_times=self.cycle_times,
addr=self.probe_address, addr=self.probe_address)
period=period,
slew=slew)
# generate control signals # generate control signals
self.sf.write("\n* Generation of control signals\n") self.sf.write("\n* Generation of control signals\n")
self.gen_csb(self.cycle_times, period, slew) self.gen_csb(self.cycle_times)
self.gen_web(self.cycle_times, period, slew) self.gen_web(self.cycle_times)
self.gen_oeb(self.cycle_times, period, slew) self.gen_oeb(self.cycle_times)
self.sf.write("\n* Generation of global clock signal\n") self.sf.write("\n* Generation of global clock signal\n")
self.stim.gen_pulse(sig_name="CLK", self.stim.gen_pulse(sig_name="CLK",
v1=self.gnd_voltage, v1=0,
v2=self.vdd_voltage, v2=self.vdd_voltage,
offset=period, offset=self.period,
period=period, period=self.period,
t_rise=slew, t_rise=self.slew,
t_fall=slew) t_fall=self.slew)
self.write_measures(period) self.write_delay_measures()
# run until the end of the cycle time # run until the end of the cycle time
self.stim.write_control(self.cycle_times[-1] + period) self.stim.write_control(self.cycle_times[-1] + self.period)
self.sf.close() self.sf.close()
def write_measures(self,period):
def write_power_stimulus(self, trim):
""" Creates a stimulus file to measure leakage power only.
This works on the *untrimmed netlist*.
"""
self.check_arguments()
# obtains list of time-points for each rising clk edge
self.obtain_cycle_times()
# creates and opens stimulus file for writing
temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
self.sf = open(temp_stim, "w")
self.sf.write("* Power stimulus for period of {0}n\n\n".format(self.period))
self.stim = stimuli.stimuli(self.sf, self.corner)
# include UNTRIMMED files in stimulus file
if trim:
self.stim.write_include(self.trim_sp_file)
else:
self.stim.write_include(self.sim_sp_file)
self.write_generic_stimulus()
# generate data and addr signals
self.sf.write("\n* Generation of data and address signals\n")
for i in range(self.word_size):
self.stim.gen_constant(sig_name="d[{0}]".format(i),
v_val=0)
for i in range(self.addr_size):
self.stim.gen_constant(sig_name="A[{0}]".format(i),
v_val=0)
# generate control signals
self.sf.write("\n* Generation of control signals\n")
self.stim.gen_constant(sig_name="CSb", v_val=self.vdd_voltage)
self.stim.gen_constant(sig_name="WEb", v_val=self.vdd_voltage)
self.stim.gen_constant(sig_name="OEb", v_val=self.vdd_voltage)
self.sf.write("\n* Generation of global clock signal\n")
self.stim.gen_constant(sig_name="CLK", v_val=0)
self.write_power_measures()
# run until the end of the cycle time
self.stim.write_control(2*self.period)
self.sf.close()
def write_delay_measures(self):
""" """
Write the measure statements to quantify the delay and power results. Write the measure statements to quantify the delay and power results.
""" """
@ -138,7 +212,7 @@ class delay():
trig_val = targ_val = 0.5 * self.vdd_voltage trig_val = targ_val = 0.5 * self.vdd_voltage
# Delay the target to measure after the negative edge # Delay the target to measure after the negative edge
self.stim.gen_meas_delay(meas_name="DELAY0", self.stim.gen_meas_delay(meas_name="DELAY_HL",
trig_name=trig_name, trig_name=trig_name,
targ_name=targ_name, targ_name=targ_name,
trig_val=trig_val, trig_val=trig_val,
@ -146,9 +220,9 @@ class delay():
trig_dir="FALL", trig_dir="FALL",
targ_dir="FALL", targ_dir="FALL",
trig_td=self.cycle_times[self.read0_cycle], trig_td=self.cycle_times[self.read0_cycle],
targ_td=self.cycle_times[self.read0_cycle]+0.5*period) targ_td=self.cycle_times[self.read0_cycle]+0.5*self.period)
self.stim.gen_meas_delay(meas_name="DELAY1", self.stim.gen_meas_delay(meas_name="DELAY_LH",
trig_name=trig_name, trig_name=trig_name,
targ_name=targ_name, targ_name=targ_name,
trig_val=trig_val, trig_val=trig_val,
@ -156,9 +230,9 @@ class delay():
trig_dir="FALL", trig_dir="FALL",
targ_dir="RISE", targ_dir="RISE",
trig_td=self.cycle_times[self.read1_cycle], trig_td=self.cycle_times[self.read1_cycle],
targ_td=self.cycle_times[self.read1_cycle]+0.5*period) targ_td=self.cycle_times[self.read1_cycle]+0.5*self.period)
self.stim.gen_meas_delay(meas_name="SLEW0", self.stim.gen_meas_delay(meas_name="SLEW_HL",
trig_name=targ_name, trig_name=targ_name,
targ_name=targ_name, targ_name=targ_name,
trig_val=0.9*self.vdd_voltage, trig_val=0.9*self.vdd_voltage,
@ -166,9 +240,9 @@ class delay():
trig_dir="FALL", trig_dir="FALL",
targ_dir="FALL", targ_dir="FALL",
trig_td=self.cycle_times[self.read0_cycle], trig_td=self.cycle_times[self.read0_cycle],
targ_td=self.cycle_times[self.read0_cycle]+0.5*period) targ_td=self.cycle_times[self.read0_cycle]+0.5*self.period)
self.stim.gen_meas_delay(meas_name="SLEW1", self.stim.gen_meas_delay(meas_name="SLEW_LH",
trig_name=targ_name, trig_name=targ_name,
targ_name=targ_name, targ_name=targ_name,
trig_val=0.1*self.vdd_voltage, trig_val=0.1*self.vdd_voltage,
@ -176,7 +250,7 @@ class delay():
trig_dir="RISE", trig_dir="RISE",
targ_dir="RISE", targ_dir="RISE",
trig_td=self.cycle_times[self.read1_cycle], trig_td=self.cycle_times[self.read1_cycle],
targ_td=self.cycle_times[self.read1_cycle]+0.5*period) targ_td=self.cycle_times[self.read1_cycle]+0.5*self.period)
# add measure statements for power # add measure statements for power
t_initial = self.cycle_times[self.write0_cycle] t_initial = self.cycle_times[self.write0_cycle]
@ -202,8 +276,23 @@ class delay():
self.stim.gen_meas_power(meas_name="READ1_POWER", self.stim.gen_meas_power(meas_name="READ1_POWER",
t_initial=t_initial, t_initial=t_initial,
t_final=t_final) t_final=t_final)
def find_feasible_period(self, load, slew): def write_power_measures(self):
"""
Write the measure statements to quantify the leakage power only.
"""
self.sf.write("\n* Measure statements for idle leakage power\n")
# add measure statements for power
t_initial = self.period
t_final = 2*self.period
self.stim.gen_meas_power(meas_name="leakage_power",
t_initial=t_initial,
t_final=t_final)
def find_feasible_period(self):
""" """
Uses an initial period and finds a feasible period before we Uses an initial period and finds a feasible period before we
run the binary search algorithm to find min period. We check if run the binary search algorithm to find min period. We check if
@ -212,7 +301,7 @@ class delay():
starting point. starting point.
""" """
feasible_period = tech.spice["feasible_period"] feasible_period = float(tech.spice["feasible_period"])
time_out = 8 time_out = 8
while True: while True:
debug.info(1, "Trying feasible period: {0}ns".format(feasible_period)) debug.info(1, "Trying feasible period: {0}ns".format(feasible_period))
@ -220,81 +309,134 @@ class delay():
if (time_out <= 0): if (time_out <= 0):
debug.error("Timed out, could not find a feasible period.",2) debug.error("Timed out, could not find a feasible period.",2)
self.period = feasible_period
(success, feasible_delay1, feasible_slew1, feasible_delay0, feasible_slew0)=self.run_simulation(feasible_period,load,slew) (success, results)=self.run_delay_simulation()
if not success: if not success:
feasible_period = 2 * feasible_period feasible_period = 2 * feasible_period
continue continue
feasible_delay_lh = results["delay_lh"]
feasible_slew_lh = results["slew_lh"]
feasible_delay_hl = results["delay_hl"]
feasible_slew_hl = results["slew_hl"]
debug.info(1, "Found feasible_period: {0}ns feasible_delay1/0 {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period, debug.info(1, "Found feasible_period: {0}ns feasible_delay {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period,
feasible_delay1, feasible_delay_lh,
feasible_delay0, feasible_delay_hl,
feasible_slew1, feasible_slew_lh,
feasible_slew0)) feasible_slew_hl))
return (feasible_period, feasible_delay1, feasible_delay0) self.period = feasible_period
return (feasible_delay_lh, feasible_delay_hl)
def run_simulation(self, period, load, slew): def run_delay_simulation(self):
""" """
This tries to simulate a period and checks if the result This tries to simulate a period and checks if the result works. If
works. If so, it returns True and the delays and slews. so, it returns True and the delays, slews, and powers. It
works on the trimmed netlist by default, so powers do not
include leakage of all cells.
""" """
# Checking from not data_value to data_value # Checking from not data_value to data_value
self.write_stimulus(period, load, slew) self.write_delay_stimulus()
self.stim.run_sim() self.stim.run_sim()
delay0 = ch.convert_to_float(ch.parse_output("timing", "delay0")) delay_hl = ch.parse_output("timing", "delay_hl")
delay1 = ch.convert_to_float(ch.parse_output("timing", "delay1")) delay_lh = ch.parse_output("timing", "delay_lh")
slew0 = ch.convert_to_float(ch.parse_output("timing", "slew0")) slew_hl = ch.parse_output("timing", "slew_hl")
slew1 = ch.convert_to_float(ch.parse_output("timing", "slew1")) slew_lh = ch.parse_output("timing", "slew_lh")
delays = (delay_hl, delay_lh, slew_hl, slew_lh)
# if it failed or the read was longer than a period
if type(delay0)!=float or type(delay1)!=float or type(slew1)!=float or type(slew0)!=float: read0_power=ch.parse_output("timing", "read0_power")
debug.info(2,"Failed simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period, write0_power=ch.parse_output("timing", "write0_power")
load, read1_power=ch.parse_output("timing", "read1_power")
slew, write1_power=ch.parse_output("timing", "write1_power")
delay0,
delay1, if not self.check_valid_delays(delays):
slew0, return (False,{})
slew1))
return (False,0,0,0,0)
# Scale delays to ns (they previously could have not been floats)
delay0 *= 1e9
delay1 *= 1e9
slew0 *= 1e9
slew1 *= 1e9
if delay0>period or delay1>period or slew0>period or slew1>period:
debug.info(2,"UNsuccessful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,
load,
slew,
delay0,
delay1,
slew0,
slew1))
return (False,0,0,0,0)
else:
debug.info(2,"Successful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,
load,
slew,
delay0,
delay1,
slew0,
slew1))
# For debug, you sometimes want to inspect each simulation. # For debug, you sometimes want to inspect each simulation.
#key=raw_input("press return to continue") #key=raw_input("press return to continue")
# Scale results to ns and mw, respectively
result = { "delay_hl" : delay_hl*1e9,
"delay_lh" : delay_lh*1e9,
"slew_hl" : slew_hl*1e9,
"slew_lh" : slew_lh*1e9,
"read0_power" : read0_power*1e3,
"read1_power" : read1_power*1e3,
"write0_power" : write0_power*1e3,
"write1_power" : write1_power*1e3}
# The delay is from the negative edge for our SRAM # The delay is from the negative edge for our SRAM
return (True,delay1,slew1,delay0,slew0) return (True,result)
def run_power_simulation(self):
"""
This simulates a disabled SRAM to get the leakage power when it is off.
"""
def find_min_period(self,feasible_period, load, slew, feasible_delay1, feasible_delay0): self.write_power_stimulus(trim=False)
self.stim.run_sim()
leakage_power=ch.parse_output("timing", "leakage_power")
debug.check(leakage_power!="Failed","Could not measure leakage power.")
self.write_power_stimulus(trim=True)
self.stim.run_sim()
trim_leakage_power=ch.parse_output("timing", "leakage_power")
debug.check(trim_leakage_power!="Failed","Could not measure leakage power.")
# For debug, you sometimes want to inspect each simulation.
#key=raw_input("press return to continue")
return (leakage_power*1e3, trim_leakage_power*1e3)
def check_valid_delays(self, (delay_hl, delay_lh, slew_hl, slew_lh)):
""" Check if the measurements are defined and if they are valid. """
# if it failed or the read was longer than a period
if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float:
debug.info(2,"Failed simulation: period {0} load {1} slew {2}, delay_hl={3}n delay_lh={4}ns slew_hl={5}n slew_lh={6}n".format(self.period,
self.load,
self.slew,
delay_hl,
delay_lh,
slew_hl,
slew_lh))
return False
# Scale delays to ns (they previously could have not been floats)
delay_hl *= 1e9
delay_lh *= 1e9
slew_hl *= 1e9
slew_lh *= 1e9
if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period:
debug.info(2,"UNsuccessful simulation: period {0} load {1} slew {2}, delay_hl={3}n delay_lh={4}ns slew_hl={5}n slew_lh={6}n".format(self.period,
self.load,
self.slew,
delay_hl,
delay_lh,
slew_hl,
slew_lh))
return False
else:
debug.info(2,"Successful simulation: period {0} load {1} slew {2}, delay_hl={3}n delay_lh={4}ns slew_hl={5}n slew_lh={6}n".format(self.period,
self.load,
self.slew,
delay_hl,
delay_lh,
slew_hl,
slew_lh))
return True
def find_min_period(self, feasible_delay_lh, feasible_delay_hl):
""" """
Searches for the smallest period with output delays being within 5% of Searches for the smallest period with output delays being within 5% of
long period. long period.
""" """
previous_period = ub_period = feasible_period previous_period = ub_period = self.period
lb_period = 0.0 lb_period = 0.0
# Binary search algorithm to find the min period (max frequency) of design # Binary search algorithm to find the min period (max frequency) of design
@ -305,11 +447,12 @@ class delay():
debug.error("Timed out, could not converge on minimum period.",2) debug.error("Timed out, could not converge on minimum period.",2)
target_period = 0.5 * (ub_period + lb_period) target_period = 0.5 * (ub_period + lb_period)
self.period = target_period
debug.info(1, "MinPeriod Search: {0}ns (ub: {1} lb: {2})".format(target_period, debug.info(1, "MinPeriod Search: {0}ns (ub: {1} lb: {2})".format(target_period,
ub_period, ub_period,
lb_period)) lb_period))
if self.try_period(target_period, load, slew, feasible_delay1, feasible_delay0): if self.try_period(feasible_delay_lh, feasible_delay_hl):
ub_period = target_period ub_period = target_period
else: else:
lb_period = target_period lb_period = target_period
@ -319,54 +462,54 @@ class delay():
return ub_period return ub_period
def try_period(self, period, load, slew, feasible_delay1, feasible_delay0): def try_period(self, feasible_delay_lh, feasible_delay_hl):
""" """
This tries to simulate a period and checks if the result This tries to simulate a period and checks if the result
works. If it does and the delay is within 5% still, it returns True. works. If it does and the delay is within 5% still, it returns True.
""" """
# Checking from not data_value to data_value # Checking from not data_value to data_value
self.write_stimulus(period,load,slew) self.write_delay_stimulus()
self.stim.run_sim() self.stim.run_sim()
delay0 = ch.convert_to_float(ch.parse_output("timing", "delay0")) delay_hl = ch.parse_output("timing", "delay_hl")
delay1 = ch.convert_to_float(ch.parse_output("timing", "delay1")) delay_lh = ch.parse_output("timing", "delay_lh")
slew0 = ch.convert_to_float(ch.parse_output("timing", "slew0")) slew_hl = ch.parse_output("timing", "slew_hl")
slew1 = ch.convert_to_float(ch.parse_output("timing", "slew1")) slew_lh = ch.parse_output("timing", "slew_lh")
# if it failed or the read was longer than a period # if it failed or the read was longer than a period
if type(delay0)!=float or type(delay1)!=float or type(slew1)!=float or type(slew0)!=float: if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float:
debug.info(2,"Invalid measures: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, debug.info(2,"Invalid measures: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
delay0, delay_hl,
delay1, delay_lh,
slew0, slew_hl,
slew1)) slew_lh))
return False return False
delay0 *= 1e9 delay_hl *= 1e9
delay1 *= 1e9 delay_lh *= 1e9
slew0 *= 1e9 slew_hl *= 1e9
slew1 *= 1e9 slew_lh *= 1e9
if delay0>period or delay1>period or slew0>period or slew1>period: if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period:
debug.info(2,"Too long delay/slew: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, debug.info(2,"Too long delay/slew: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
delay0, delay_hl,
delay1, delay_lh,
slew0, slew_hl,
slew1)) slew_lh))
return False return False
else: else:
if not ch.relative_compare(delay1,feasible_delay1,error_tolerance=0.05): if not ch.relative_compare(delay_lh,feasible_delay_lh,error_tolerance=0.05):
debug.info(2,"Delay too big {0} vs {1}".format(delay1,feasible_delay1)) debug.info(2,"Delay too big {0} vs {1}".format(delay_lh,feasible_delay_lh))
return False return False
elif not ch.relative_compare(delay0,feasible_delay0,error_tolerance=0.05): elif not ch.relative_compare(delay_hl,feasible_delay_hl,error_tolerance=0.05):
debug.info(2,"Delay too big {0} vs {1}".format(delay0,feasible_delay0)) debug.info(2,"Delay too big {0} vs {1}".format(delay_hl,feasible_delay_hl))
return False return False
#key=raw_input("press return to continue") #key=raw_input("press return to continue")
debug.info(2,"Successful period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, debug.info(2,"Successful period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
delay0, delay_hl,
delay1, delay_lh,
slew0, slew_hl,
slew1)) slew_lh))
return True return True
def set_probe(self,probe_address, probe_data): def set_probe(self,probe_address, probe_data):
@ -375,12 +518,35 @@ class delay():
self.probe_address = probe_address self.probe_address = probe_address
self.probe_data = probe_data self.probe_data = probe_data
self.prepare_netlist()
def prepare_netlist(self):
""" Prepare a trimmed netlist and regular netlist. """
# Set up to trim the netlist here if that is enabled
if OPTS.trim_netlist:
self.trim_sp_file = "{}reduced.sp".format(OPTS.openram_temp)
self.trimsp=trim_spice(self.sp_file, self.trim_sp_file)
self.trimsp.set_configuration(self.num_banks,
self.num_rows,
self.num_cols,
self.word_size)
self.trimsp.trim(self.probe_address,self.probe_data)
else:
# The non-reduced netlist file when it is disabled
self.trim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
# The non-reduced netlist file for power simulation
self.sim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
# Make a copy in temp for debugging
shutil.copy(self.sp_file, self.sim_sp_file)
def analyze(self,probe_address, probe_data, slews, loads): def analyze(self,probe_address, probe_data, slews, loads):
"""main function to calculate the min period for a low_to_high """
transistion and a high_to_low transistion returns a dictionary Main function to characterize an SRAM for a table. Computes both delay and power characterization.
that contains all both the min period and associated delays
Dictionary Keys: min_period1, delay1, min_period0, delay0
""" """
self.set_probe(probe_address, probe_data) self.set_probe(probe_address, probe_data)
@ -388,58 +554,62 @@ class delay():
# This is for debugging a full simulation # This is for debugging a full simulation
# debug.info(0,"Debug simulation running...") # debug.info(0,"Debug simulation running...")
# target_period=50.0 # target_period=50.0
# feasible_delay1=0.059083183 # feasible_delay_lh=0.059083183
# feasible_delay0=0.17953789 # feasible_delay_hl=0.17953789
# load=1.6728 # load=1.6728
# slew=0.04 # slew=0.04
# self.try_period(target_period, load, slew, feasible_delay1, feasible_delay0) # self.try_period(target_period, feasible_delay_lh, feasible_delay_hl)
# sys.exit(1) # sys.exit(1)
(feasible_period, feasible_delay1, feasible_delay0) = self.find_feasible_period(max(loads), max(slews))
debug.check(feasible_delay1>0,"Negative delay may not be possible")
debug.check(feasible_delay0>0,"Negative delay may not be possible")
# The power variables are just scalars. These use the final feasible period simulation # 1) Find a feasible period and it's corresponding delays using the trimmed array.
# which should have worked. self.load=max(loads)
read0_power=ch.convert_to_float(ch.parse_output("timing", "read0_power")) self.slew=max(slews)
write0_power=ch.convert_to_float(ch.parse_output("timing", "write0_power")) (feasible_delay_lh, feasible_delay_hl) = self.find_feasible_period()
read1_power=ch.convert_to_float(ch.parse_output("timing", "read1_power")) debug.check(feasible_delay_lh>0,"Negative delay may not be possible")
write1_power=ch.convert_to_float(ch.parse_output("timing", "write1_power")) debug.check(feasible_delay_hl>0,"Negative delay may not be possible")
LH_delay = [] # 2) Measure the delay, slew and power for all slew/load pairs.
HL_delay = [] # Make a list for each type of measurement to append results to
LH_slew = [] char_data = {}
HL_slew = [] for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power",
"read1_power", "write0_power", "write1_power", "leakage_power"]:
char_data[m]=[]
# 2a) Find the leakage power of the trimmmed and UNtrimmed arrays.
(full_array_leakage, trim_array_leakage)=self.run_power_simulation()
char_data["leakage_power"]=full_array_leakage
for slew in slews: for slew in slews:
for load in loads: for load in loads:
(success, delay1, slew1, delay0, slew0) = self.run_simulation(feasible_period, load, slew) self.set_load_slew(load,slew)
debug.check(success,"Couldn't run a simulation. slew={0} load={1}\n".format(slew,load)) # 2c) Find the delay, dynamic power, and leakage power of the trimmed array.
LH_delay.append(delay1) (success, delay_results) = self.run_delay_simulation()
HL_delay.append(delay0) debug.check(success,"Couldn't run a simulation. slew={0} load={1}\n".format(self.slew,self.load))
LH_slew.append(slew1) for k,v in delay_results.items():
HL_slew.append(slew0) if "power" in k:
# Subtract partial array leakage and add full array leakage for the power measures
# finds the minimum period without degrading the delays by X% char_data[k].append(v - trim_array_leakage + full_array_leakage)
min_period = self.find_min_period(feasible_period, max(loads), max(slews), feasible_delay1, feasible_delay0) else:
char_data[k].append(v)
# 3) Finds the minimum period without degrading the delays by X%
self.set_load_slew(max(loads),max(slews))
min_period = self.find_min_period(feasible_delay_lh, feasible_delay_hl)
debug.check(type(min_period)==float,"Couldn't find minimum period.") debug.check(type(min_period)==float,"Couldn't find minimum period.")
debug.info(1, "Min Period: {0}n with a delay of {1} / {2}".format(min_period, feasible_delay1, feasible_delay0)) debug.info(1, "Min Period: {0}n with a delay of {1} / {2}".format(min_period, feasible_delay_lh, feasible_delay_hl))
# 4) Pack up the final measurements
char_data["min_period"] = ch.round_time(min_period)
return char_data
data = {"min_period": ch.round_time(min_period),
"delay1": LH_delay,
"delay0": HL_delay,
"slew1": LH_slew,
"slew0": HL_slew,
"read0_power": read0_power*1e3,
"read1_power": read1_power*1e3,
"write0_power": write0_power*1e3,
"write1_power": write1_power*1e3
}
return data
def obtain_cycle_times(self):
def obtain_cycle_times(self, period):
"""Returns a list of key time-points [ns] of the waveform (each rising edge) """Returns a list of key time-points [ns] of the waveform (each rising edge)
of the cycles to do a timing evaluation. The last time is the end of the simulation of the cycles to do a timing evaluation. The last time is the end of the simulation
and does not need a rising edge.""" and does not need a rising edge."""
@ -451,135 +621,135 @@ class delay():
# idle cycle, no operation # idle cycle, no operation
msg = "Idle cycle (no clock)" msg = "Idle cycle (no clock)"
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(0, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(0,
t_current, t_current,
msg)) msg))
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
t_current += period t_current += self.period
# One period # One period
msg = "W data 1 address 11..11 to initialize cell" msg = "W data 1 address 11..11 to initialize cell"
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
t_current, t_current,
msg)) msg))
t_current += period t_current += self.period
# One period # One period
msg = "W data 0 address 11..11 (to ensure a write of value works)" msg = "W data 0 address 11..11 (to ensure a write of value works)"
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
self.write0_cycle=len(self.cycle_times)-1 self.write0_cycle=len(self.cycle_times)-1
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
t_current, t_current,
msg)) msg))
t_current += period t_current += self.period
# One period # One period
msg = "W data 1 address 00..00 (to clear bus caps)" msg = "W data 1 address 00..00 (to clear bus caps)"
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
t_current, t_current,
msg)) msg))
t_current += period t_current += self.period
# One period # One period
msg = "R data 0 address 11..11 to check W0 worked" msg = "R data 0 address 11..11 to check W0 worked"
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
self.read0_cycle=len(self.cycle_times)-1 self.read0_cycle=len(self.cycle_times)-1
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
t_current, t_current,
msg)) msg))
t_current += period t_current += self.period
# One period # One period
msg = "Idle cycle" msg = "Idle cycle (Read addr 00..00)"
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
t_current, t_current,
msg)) msg))
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
t_current += period self.idle_cycle=len(self.cycle_times)-1
t_current += self.period
# One period # One period
msg = "W data 1 address 11..11 (to ensure a write of value worked)" msg = "W data 1 address 11..11 (to ensure a write of value worked)"
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
self.write1_cycle=len(self.cycle_times)-1 self.write1_cycle=len(self.cycle_times)-1
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
t_current, t_current,
msg)) msg))
t_current += period t_current += self.period
# One period # One period
msg = "W data 0 address 00..00 (to clear bus caps)" msg = "W data 0 address 00..00 (to clear bus caps)"
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
t_current, t_current,
msg)) msg))
t_current += period t_current += self.period
# One period # One period
msg = "R data 1 address 11..11 to check W1 worked" msg = "R data 1 address 11..11 to check W1 worked"
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
self.read1_cycle=len(self.cycle_times)-1 self.read1_cycle=len(self.cycle_times)-1
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
t_current, t_current,
msg)) msg))
t_current += period t_current += self.period
# One period # One period
msg = "Idle cycle" msg = "Idle cycle (Read addr 11..11)"
self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1,
t_current, t_current,
msg)) msg))
self.cycle_times.append(t_current) self.cycle_times.append(t_current)
t_current += period t_current += self.period
def analytical_model(self,sram, slews, loads): def analytical_delay(self,sram, slews, loads):
""" Just return the analytical model results for the SRAM. """ Just return the analytical model results for the SRAM.
""" """
LH_delay = [] delay_lh = []
HL_delay = [] delay_hl = []
LH_slew = [] slew_lh = []
HL_slew = [] slew_hl = []
for slew in slews: for slew in slews:
for load in loads: for load in loads:
bank_delay = sram.analytical_delay(slew,load) self.set_load_slew(load,slew)
# Convert from ps to ns bank_delay = sram.analytical_delay(self.slew,self.load)
LH_delay.append(bank_delay.delay/1e3) delay_lh.append(bank_delay.delay/1e3)
HL_delay.append(bank_delay.delay/1e3) delay_hl.append(bank_delay.delay/1e3)
LH_slew.append(bank_delay.slew/1e3) slew_lh.append(bank_delay.slew/1e3)
HL_slew.append(bank_delay.slew/1e3) slew_hl.append(bank_delay.slew/1e3)
power = sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load) power = sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load)
#convert from nW to mW #convert from nW to mW
power.dynamic /= 1e6 power.dynamic /= 1e6
power.leakage /= 1e6 power.leakage /= 1e6
debug.info(1,"Dynamic Power: {0} mW".format(power.dynamic)) debug.info(1,"Dynamic Power: {0} mW".format(power.dynamic))
debug.info(1,"Leakage Power: {0} mW".format(power.leakage)) debug.info(1,"Leakage Power: {0} mW".format(power.leakage))
#print "Dynamic: ",power.dynamic," nW"
#print "Leakage: ",power.leakage," nW"
data = {"min_period": 0, data = {"min_period": 0,
"delay1": LH_delay, "delay_lh": delay_lh,
"delay0": HL_delay, "delay_hl": delay_hl,
"slew1": LH_slew, "slew_lh": slew_lh,
"slew0": HL_slew, "slew_hl": slew_hl,
"read0_power": power.dynamic, "read0_power": power.dynamic,
"read1_power": power.leakage, "read1_power": power.dynamic,
"write0_power": power.dynamic, "write0_power": power.dynamic,
"write1_power": power.leakage "write1_power": power.dynamic,
"leakage_power": power.leakage
} }
return data return data
def gen_data(self, clk_times, sig_name, period, slew): def gen_data(self, clk_times, sig_name):
""" Generates the PWL data inputs for a simulation timing test. """ """ Generates the PWL data inputs for a simulation timing test. """
# values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP # values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP
# we are asserting the opposite value on the other side of the tx gate during # we are asserting the opposite value on the other side of the tx gate during
# the read to be "worst case". Otherwise, it can actually assist the read. # the read to be "worst case". Otherwise, it can actually assist the read.
values = [0, 1, 0, 1, 1, 1, 1, 0, 0, 0 ] values = [0, 1, 0, 1, 1, 1, 1, 0, 0, 0 ]
self.stim.gen_pwl(sig_name, clk_times, values, period, slew, 0.05) self.stim.gen_pwl(sig_name, clk_times, values, self.period, self.slew, 0.05)
def gen_addr(self, clk_times, addr, period, slew): def gen_addr(self, clk_times, addr):
""" """
Generates the address inputs for a simulation timing test. Generates the address inputs for a simulation timing test.
This alternates between all 1's and all 0's for the address. This alternates between all 1's and all 0's for the address.
@ -591,34 +761,34 @@ class delay():
for i in range(len(addr)): for i in range(len(addr)):
sig_name = "A[{0}]".format(i) sig_name = "A[{0}]".format(i)
if addr[i]=="1": if addr[i]=="1":
self.stim.gen_pwl(sig_name, clk_times, ones_values, period, slew, 0.05) self.stim.gen_pwl(sig_name, clk_times, ones_values, self.period, self.slew, 0.05)
else: else:
self.stim.gen_pwl(sig_name, clk_times, zero_values, period, slew, 0.05) self.stim.gen_pwl(sig_name, clk_times, zero_values, self.period, self.slew, 0.05)
def gen_csb(self, clk_times, period, slew): def gen_csb(self, clk_times):
""" Generates the PWL CSb signal """ """ Generates the PWL CSb signal """
# values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP # values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP
# Keep CSb asserted in NOP for measuring >1 period # Keep CSb asserted in NOP for measuring >1 period
values = [1, 0, 0, 0, 0, 0, 0, 0, 0, 0] values = [1, 0, 0, 0, 0, 0, 0, 0, 0, 0]
self.stim.gen_pwl("csb", clk_times, values, period, slew, 0.05) self.stim.gen_pwl("csb", clk_times, values, self.period, self.slew, 0.05)
def gen_web(self, clk_times, period, slew): def gen_web(self, clk_times):
""" Generates the PWL WEb signal """ """ Generates the PWL WEb signal """
# values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP # values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP
# Keep WEb deasserted in NOP for measuring >1 period # Keep WEb deasserted in NOP for measuring >1 period
values = [1, 0, 0, 0, 1, 1, 0, 0, 1, 1] values = [1, 0, 0, 0, 1, 1, 0, 0, 1, 1]
self.stim.gen_pwl("web", clk_times, values, period, slew, 0.05) self.stim.gen_pwl("web", clk_times, values, self.period, self.slew, 0.05)
# Keep acc_en deasserted in NOP for measuring >1 period # Keep acc_en deasserted in NOP for measuring >1 period
values = [1, 0, 0, 0, 1, 1, 0, 0, 1, 1] values = [1, 0, 0, 0, 1, 1, 0, 0, 1, 1]
self.stim.gen_pwl("acc_en", clk_times, values, period, slew, 0) self.stim.gen_pwl("acc_en", clk_times, values, self.period, self.slew, 0)
values = [0, 1, 1, 1, 0, 0, 1, 1, 0, 0] values = [0, 1, 1, 1, 0, 0, 1, 1, 0, 0]
self.stim.gen_pwl("acc_en_inv", clk_times, values, period, slew, 0) self.stim.gen_pwl("acc_en_inv", clk_times, values, self.period, self.slew, 0)
def gen_oeb(self, clk_times, period, slew): def gen_oeb(self, clk_times):
""" Generates the PWL WEb signal """ """ Generates the PWL WEb signal """
# values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP # values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP
# Keep OEb asserted in NOP for measuring >1 period # Keep OEb asserted in NOP for measuring >1 period
values = [1, 1, 1, 1, 0, 0, 1, 1, 0, 0] values = [1, 1, 1, 1, 0, 0, 1, 1, 0, 0]
self.stim.gen_pwl("oeb", clk_times, values, period, slew, 0.05) self.stim.gen_pwl("oeb", clk_times, values, self.period, self.slew, 0.05)

183
compiler/characterizer/lib.py
View File

@ -1,4 +1,4 @@
import os,sys,re,shutil import os,sys,re
import debug import debug
import math import math
import setup_hold import setup_hold
@ -6,7 +6,6 @@ import delay
import charutils as ch import charutils as ch
import tech import tech
import numpy as np import numpy as np
from trim_spice import trim_spice
from globals import OPTS from globals import OPTS
class lib: class lib:
@ -18,30 +17,12 @@ class lib:
self.sp_file = sp_file self.sp_file = sp_file
self.use_model = use_model self.use_model = use_model
self.prepare_netlist()
self.prepare_tables() self.prepare_tables()
self.create_corners() self.create_corners()
self.characterize_corners() self.characterize_corners()
def prepare_netlist(self):
""" Determine whether to use regular or trimmed netlist. """
# Set up to trim the netlist here if that is enabled
if OPTS.trim_netlist:
self.sim_sp_file = "{}reduced.sp".format(OPTS.openram_temp)
self.trimsp=trim_spice(self.sp_file, self.sim_sp_file)
self.trimsp.set_configuration(self.sram.num_banks,
self.sram.num_rows,
self.sram.num_cols,
self.sram.word_size)
else:
# Else, use the non-reduced netlist file for simulation
self.sim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
# Make a copy in temp for debugging
shutil.copy(self.sp_file, self.sim_sp_file)
def prepare_tables(self): def prepare_tables(self):
""" Determine the load/slews if they aren't specified in the config file. """ """ Determine the load/slews if they aren't specified in the config file. """
@ -49,7 +30,7 @@ class lib:
#self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8]) #self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
self.load_scales = np.array([0.25, 1, 8]) self.load_scales = np.array([0.25, 1, 8])
#self.load_scales = np.array([0.25, 1]) #self.load_scales = np.array([0.25, 1])
self.load = tech.spice["msflop_in_cap"] self.load = tech.spice["dff_in_cap"]
self.loads = self.load_scales*self.load self.loads = self.load_scales*self.load
debug.info(1,"Loads: {0}".format(self.loads)) debug.info(1,"Loads: {0}".format(self.loads))
@ -78,7 +59,7 @@ class lib:
proc, proc,
volt, volt,
temp) temp)
self.corner_name = self.corner_name.replace(".","") # Remove decimals self.corner_name = self.corner_name.replace(".","p") # Remove decimals
lib_name = self.out_dir+"{}.lib".format(self.corner_name) lib_name = self.out_dir+"{}.lib".format(self.corner_name)
# A corner is a tuple of PVT # A corner is a tuple of PVT
@ -93,10 +74,15 @@ class lib:
self.lib = open(lib_name, "w") self.lib = open(lib_name, "w")
debug.info(1,"Writing to {0}".format(lib_name)) debug.info(1,"Writing to {0}".format(lib_name))
self.characterize() self.characterize()
self.lib.close()
def characterize(self): def characterize(self):
""" Characterize the current corner. """ """ Characterize the current corner. """
self.compute_delay()
self.compute_setup_hold()
self.write_header() self.write_header()
self.write_data_bus() self.write_data_bus()
@ -106,8 +92,13 @@ class lib:
self.write_control_pins() self.write_control_pins()
self.write_clk() self.write_clk()
self.write_footer()
self.lib.close() def write_footer(self):
""" Write the footer """
self.lib.write("}\n")
def write_header(self): def write_header(self):
""" Write the header information """ """ Write the header information """
@ -119,7 +110,7 @@ class lib:
self.write_defaults() self.write_defaults()
self.write_LUT_templates() self.write_LUT_templates()
self.lib.write(" default_operating_conditions : TT; \n") self.lib.write(" default_operating_conditions : OC; \n")
self.write_bus() self.write_bus()
@ -127,14 +118,21 @@ class lib:
self.lib.write("{\n") self.lib.write("{\n")
self.lib.write(" memory(){ \n") self.lib.write(" memory(){ \n")
self.lib.write(" type : ram;\n") self.lib.write(" type : ram;\n")
self.lib.write(" address_width : {0};\n".format(self.sram.addr_size)) self.lib.write(" address_width : {};\n".format(self.sram.addr_size))
self.lib.write(" word_width : {0};\n".format(self.sram.word_size)) self.lib.write(" word_width : {};\n".format(self.sram.word_size))
self.lib.write(" }\n") self.lib.write(" }\n")
self.lib.write(" interface_timing : true;\n") self.lib.write(" interface_timing : true;\n")
self.lib.write(" dont_use : true;\n") self.lib.write(" dont_use : true;\n")
self.lib.write(" map_only : true;\n") self.lib.write(" map_only : true;\n")
self.lib.write(" dont_touch : true;\n") self.lib.write(" dont_touch : true;\n")
self.lib.write(" area : {0};\n\n".format(self.sram.width * self.sram.height)) self.lib.write(" area : {};\n\n".format(self.sram.width * self.sram.height))
# Leakage is included in dynamic when macro is enabled
self.lib.write(" leakage_power () {\n")
self.lib.write(" when : \"CSb\";\n")
self.lib.write(" value : {};\n".format(self.char_results["leakage_power"]))
self.lib.write(" }\n")
self.lib.write(" cell_leakage_power : {};\n".format(0))
def write_units(self): def write_units(self):
@ -147,7 +145,8 @@ class lib:
self.lib.write(" capacitive_load_unit(1 ,fF) ;\n") self.lib.write(" capacitive_load_unit(1 ,fF) ;\n")
self.lib.write(" leakage_power_unit : \"1mW\" ;\n") self.lib.write(" leakage_power_unit : \"1mW\" ;\n")
self.lib.write(" pulling_resistance_unit :\"1kohm\" ;\n") self.lib.write(" pulling_resistance_unit :\"1kohm\" ;\n")
self.lib.write(" operating_conditions({}){{\n".format(self.process)) self.lib.write(" operating_conditions(OC){\n")
self.lib.write(" process : {} ;\n".format(1.0)) # How to use TT, FF, SS?
self.lib.write(" voltage : {} ;\n".format(self.voltage)) self.lib.write(" voltage : {} ;\n".format(self.voltage))
self.lib.write(" temperature : {};\n".format(self.temperature)) self.lib.write(" temperature : {};\n".format(self.temperature))
self.lib.write(" }\n\n") self.lib.write(" }\n\n")
@ -164,6 +163,10 @@ class lib:
self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n") self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n")
self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n") self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n")
self.lib.write(" nom_voltage : {};\n".format(tech.spice["nom_supply_voltage"]))
self.lib.write(" nom_temperature : {};\n".format(tech.spice["nom_temperature"]))
self.lib.write(" nom_process : {};\n".format(1.0))
self.lib.write(" default_cell_leakage_power : 0.0 ;\n") self.lib.write(" default_cell_leakage_power : 0.0 ;\n")
self.lib.write(" default_leakage_power_density : 0.0 ;\n") self.lib.write(" default_leakage_power_density : 0.0 ;\n")
self.lib.write(" default_input_pin_cap : 1.0 ;\n") self.lib.write(" default_input_pin_cap : 1.0 ;\n")
@ -267,8 +270,6 @@ class lib:
def write_FF_setuphold(self): def write_FF_setuphold(self):
""" Adds Setup and Hold timing results""" """ Adds Setup and Hold timing results"""
self.compute_setup_hold()
self.lib.write(" timing(){ \n") self.lib.write(" timing(){ \n")
self.lib.write(" timing_type : setup_rising; \n") self.lib.write(" timing_type : setup_rising; \n")
self.lib.write(" related_pin : \"clk\"; \n") self.lib.write(" related_pin : \"clk\"; \n")
@ -299,12 +300,12 @@ class lib:
def write_data_bus(self): def write_data_bus(self):
""" Adds data bus timing results.""" """ Adds data bus timing results."""
self.compute_delay()
self.lib.write(" bus(DATA){\n") self.lib.write(" bus(DATA){\n")
self.lib.write(" bus_type : DATA; \n") self.lib.write(" bus_type : DATA; \n")
self.lib.write(" direction : inout; \n") self.lib.write(" direction : inout; \n")
self.lib.write(" max_capacitance : {0}; \n".format(8*tech.spice["msflop_in_cap"])) # This is conservative, but limit to range that we characterized.
self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads)))
self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads)))
self.lib.write(" three_state : \"!OEb & !clk\"; \n") self.lib.write(" three_state : \"!OEb & !clk\"; \n")
self.lib.write(" memory_write(){ \n") self.lib.write(" memory_write(){ \n")
self.lib.write(" address : ADDR; \n") self.lib.write(" address : ADDR; \n")
@ -313,53 +314,29 @@ class lib:
self.lib.write(" memory_read(){ \n") self.lib.write(" memory_read(){ \n")
self.lib.write(" address : ADDR; \n") self.lib.write(" address : ADDR; \n")
self.lib.write(" }\n") self.lib.write(" }\n")
self.lib.write(" pin(DATA[{0}:0])".format(self.sram.word_size - 1))
self.lib.write("{\n")
self.lib.write(" internal_power(){\n")
self.lib.write(" when : \"OEb & !clk\"; \n")
self.lib.write(" rise_power(scalar){\n")
self.lib.write(" values(\"{0}\");\n".format(self.delay["write1_power"]))
self.lib.write(" }\n")
self.lib.write(" fall_power(scalar){\n")
self.lib.write(" values(\"{0}\");\n".format(self.delay["write0_power"]))
self.lib.write(" }\n")
self.lib.write(" }\n")
self.lib.write(" pin(DATA[{0}:0]){{\n".format(self.sram.word_size - 1))
self.write_FF_setuphold() self.write_FF_setuphold()
self.lib.write(" internal_power(){\n")
self.lib.write(" when : \"!OEb & !clk\"; \n")
self.lib.write(" rise_power(scalar){\n")
self.lib.write(" values(\"{0}\");\n".format(self.delay["read1_power"]))
self.lib.write(" }\n")
self.lib.write(" fall_power(scalar){\n")
self.lib.write(" values(\"{0}\");\n".format(self.delay["read0_power"]))
self.lib.write(" }\n")
self.lib.write(" }\n")
self.lib.write(" timing(){ \n") self.lib.write(" timing(){ \n")
self.lib.write(" timing_sense : non_unate; \n") self.lib.write(" timing_sense : non_unate; \n")
self.lib.write(" related_pin : \"clk\"; \n") self.lib.write(" related_pin : \"clk\"; \n")
self.lib.write(" timing_type : falling_edge; \n") self.lib.write(" timing_type : falling_edge; \n")
self.lib.write(" cell_rise(CELL_TABLE) {\n") self.lib.write(" cell_rise(CELL_TABLE) {\n")
rounded_values = map(ch.round_time,self.delay["delay1"]) self.write_values(self.char_results["delay_lh"],len(self.loads)," ")
self.write_values(rounded_values,len(self.loads)," ") self.lib.write(" }\n") # rise delay
self.lib.write(" }\n")
self.lib.write(" cell_fall(CELL_TABLE) {\n") self.lib.write(" cell_fall(CELL_TABLE) {\n")
rounded_values = map(ch.round_time,self.delay["delay0"]) self.write_values(self.char_results["delay_hl"],len(self.loads)," ")
self.write_values(rounded_values,len(self.loads)," ") self.lib.write(" }\n") # fall delay
self.lib.write(" }\n") self.lib.write(" rise_transition(CELL_TABLE) {\n")
self.lib.write(" rise_transition(CELL_TABLE) {\n") self.write_values(self.char_results["slew_lh"],len(self.loads)," ")
rounded_values = map(ch.round_time,self.delay["slew1"]) self.lib.write(" }\n") # rise trans
self.write_values(rounded_values,len(self.loads)," ") self.lib.write(" fall_transition(CELL_TABLE) {\n")
self.lib.write(" }\n") self.write_values(self.char_results["slew_hl"],len(self.loads)," ")
self.lib.write(" fall_transition(CELL_TABLE) {\n") self.lib.write(" }\n") # fall trans
rounded_values = map(ch.round_time,self.delay["slew0"]) self.lib.write(" }\n") # timing
self.write_values(rounded_values,len(self.loads)," ") self.lib.write(" }\n") # pin
self.lib.write(" }\n") self.lib.write(" }\n\n") # bus
self.lib.write(" }\n")
self.lib.write(" }\n")
self.lib.write(" }\n\n")
def write_addr_bus(self): def write_addr_bus(self):
@ -368,9 +345,8 @@ class lib:
self.lib.write(" bus(ADDR){\n") self.lib.write(" bus(ADDR){\n")
self.lib.write(" bus_type : ADDR; \n") self.lib.write(" bus_type : ADDR; \n")
self.lib.write(" direction : input; \n") self.lib.write(" direction : input; \n")
self.lib.write(" capacitance : {0}; \n".format(tech.spice["msflop_in_cap"])) self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
self.lib.write(" max_transition : {0};\n".format(self.slews[-1])) self.lib.write(" max_transition : {0};\n".format(self.slews[-1]))
self.lib.write(" fanout_load : 1.000000;\n")
self.lib.write(" pin(ADDR[{0}:0])".format(self.sram.addr_size - 1)) self.lib.write(" pin(ADDR[{0}:0])".format(self.sram.addr_size - 1))
self.lib.write("{\n") self.lib.write("{\n")
@ -387,7 +363,7 @@ class lib:
self.lib.write(" pin({0})".format(i)) self.lib.write(" pin({0})".format(i))
self.lib.write("{\n") self.lib.write("{\n")
self.lib.write(" direction : input; \n") self.lib.write(" direction : input; \n")
self.lib.write(" capacitance : {0}; \n".format(tech.spice["msflop_in_cap"])) self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
self.write_FF_setuphold() self.write_FF_setuphold()
self.lib.write(" }\n\n") self.lib.write(" }\n\n")
@ -395,14 +371,50 @@ class lib:
def write_clk(self): def write_clk(self):
""" Adds clk pin timing results.""" """ Adds clk pin timing results."""
self.compute_delay()
self.lib.write(" pin(clk){\n") self.lib.write(" pin(clk){\n")
self.lib.write(" clock : true;\n") self.lib.write(" clock : true;\n")
self.lib.write(" direction : input; \n") self.lib.write(" direction : input; \n")
self.lib.write(" capacitance : {0}; \n".format(tech.spice["msflop_in_cap"])) # This should actually be a min inverter cap, but ok...
min_pulse_width = ch.round_time(self.delay["min_period"])/2.0 self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
min_period = ch.round_time(self.delay["min_period"])
# Find the average power of 1 and 0 bits for writes and reads over all loads/slews
# Could make it a table, but this is fine for now.
avg_write_power = np.mean(self.char_results["write1_power"] + self.char_results["write0_power"])
avg_read_power = np.mean(self.char_results["read1_power"] + self.char_results["read0_power"])
# Equally divide read/write power between first and second half of clock period
self.lib.write(" internal_power(){\n")
self.lib.write(" when : \"!CSb & clk & !WEb\"; \n")
self.lib.write(" rise_power(scalar){\n")
self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
self.lib.write(" }\n")
self.lib.write(" fall_power(scalar){\n")
self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
self.lib.write(" }\n")
self.lib.write(" }\n")
self.lib.write(" internal_power(){\n")
self.lib.write(" when : \"!CSb & !clk & WEb\"; \n")
self.lib.write(" rise_power(scalar){\n")
self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
self.lib.write(" }\n")
self.lib.write(" fall_power(scalar){\n")
self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
self.lib.write(" }\n")
self.lib.write(" }\n")
# Have 0 internal power when disabled, this will be represented as leakage power.
self.lib.write(" internal_power(){\n")
self.lib.write(" when : \"CSb\"; \n")
self.lib.write(" rise_power(scalar){\n")
self.lib.write(" values(\"0\");\n")
self.lib.write(" }\n")
self.lib.write(" fall_power(scalar){\n")
self.lib.write(" values(\"0\");\n")
self.lib.write(" }\n")
self.lib.write(" }\n")
min_pulse_width = ch.round_time(self.char_results["min_period"])/2.0
min_period = ch.round_time(self.char_results["min_period"])
self.lib.write(" timing(){ \n") self.lib.write(" timing(){ \n")
self.lib.write(" timing_type :\"min_pulse_width\"; \n") self.lib.write(" timing_type :\"min_pulse_width\"; \n")
self.lib.write(" related_pin : clk; \n") self.lib.write(" related_pin : clk; \n")
@ -425,23 +437,20 @@ class lib:
self.lib.write(" }\n") self.lib.write(" }\n")
self.lib.write(" }\n") self.lib.write(" }\n")
self.lib.write(" }\n") self.lib.write(" }\n")
self.lib.write("}\n")
def compute_delay(self): def compute_delay(self):
""" Do the analysis if we haven't characterized the SRAM yet """ """ Do the analysis if we haven't characterized the SRAM yet """
try: try:
self.d self.d
except AttributeError: except AttributeError:
self.d = delay.delay(self.sram, self.sim_sp_file, self.corner) self.d = delay.delay(self.sram, self.sp_file, self.corner)
if self.use_model: if self.use_model:
self.delay = self.d.analytical_model(self.sram,self.slews,self.loads) self.char_results = self.d.analytical_delay(self.sram,self.slews,self.loads)
else: else:
probe_address = "1" * self.sram.addr_size probe_address = "1" * self.sram.addr_size
probe_data = self.sram.word_size - 1 probe_data = self.sram.word_size - 1
# We must trim based on a specific address and data bit self.char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
if OPTS.trim_netlist:
self.trimsp.trim(probe_address,probe_data)
self.delay = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
def compute_setup_hold(self): def compute_setup_hold(self):
""" Do the analysis if we haven't characterized a FF yet """ """ Do the analysis if we haven't characterized a FF yet """
@ -451,7 +460,7 @@ class lib:
except AttributeError: except AttributeError:
self.sh = setup_hold.setup_hold(self.corner) self.sh = setup_hold.setup_hold(self.corner)
if self.use_model: if self.use_model:
self.times = self.sh.analytical_model(self.slews,self.loads) self.times = self.sh.analytical_setuphold(self.slews,self.loads)
else: else:
self.times = self.sh.analyze(self.slews,self.slews) self.times = self.sh.analyze(self.slews,self.slews)

2
compiler/characterizer/setup_hold.py
View File

@ -299,7 +299,7 @@ class setup_hold():
} }
return times return times
def analytical_model(self,related_slews, constrained_slews): def analytical_setuphold(self,related_slews, constrained_slews):
""" Just return the fixed setup/hold times from the technology. """ Just return the fixed setup/hold times from the technology.
""" """
LH_setup = [] LH_setup = []

1
compiler/characterizer/stimuli.py
View File

@ -286,6 +286,7 @@ class stimuli():
OPTS.openram_temp) OPTS.openram_temp)
valid_retcode=0 valid_retcode=0
else: else:
# ngspice 27+ supports threading with "set num_threads=4" in the stimulus file or a .spiceinit
cmd = "{0} -b -o {2}timing.lis {1}".format(OPTS.spice_exe, cmd = "{0} -b -o {2}timing.lis {1}".format(OPTS.spice_exe,
temp_stim, temp_stim,
OPTS.openram_temp) OPTS.openram_temp)

2
compiler/example_config_freepdk45.py
View File

@ -1,5 +1,5 @@
word_size = 2 word_size = 2
num_words = 128 num_words = 16
num_banks = 1 num_banks = 1
tech_name = "freepdk45" tech_name = "freepdk45"

33
compiler/gdsMill/gdsMill/vlsiLayout.py
View File

@ -772,29 +772,36 @@ class VlsiLayout:
return boundaries return boundaries
def getPinInStructure(self,coordinates,layer,Structure): def getPinInStructure(self,coordinates,layer,structure):
""" """
Go through all the shapes in a structure and return the list of shapes Go through all the shapes in a structure and return the list of shapes
that the label coordinates are inside. that the label coordinates are inside.
""" """
StructureName=Structure[0]
StructureOrigin=[Structure[1][0],Structure[1][1]] # check if this is a rectangle
StructureuVector=[Structure[2][0],Structure[2][1],Structure[2][2]] structureName=structure[0]
StructurevVector=[Structure[3][0],Structure[3][1],Structure[3][2]] structureOrigin=[structure[1][0],structure[1][1]]
structureuVector=[structure[2][0],structure[2][1],structure[2][2]]
structurevVector=[structure[3][0],structure[3][1],structure[3][2]]
boundaries = [] boundaries = []
for boundary in self.structures[str(StructureName)].boundaries: for boundary in self.structures[str(structureName)].boundaries:
# Pin enclosures only work on rectangular pins so ignore any non rectangle
# This may report not finding pins, but the user should fix this by adding a rectangle.
if len(boundary.coordinates)!=5:
continue
if layer==boundary.drawingLayer: if layer==boundary.drawingLayer:
left_bottom=boundary.coordinates[0] left_bottom=boundary.coordinates[0]
right_top=boundary.coordinates[2] right_top=boundary.coordinates[2]
MetalBoundary=[left_bottom[0],left_bottom[1],right_top[0],right_top[1]] # Rectangle is [leftx, bottomy, rightx, topy].
MetalBoundary=self.transformRectangle(MetalBoundary,StructureuVector,StructurevVector) boundaryRect=[left_bottom[0],left_bottom[1],right_top[0],right_top[1]]
MetalBoundary=[MetalBoundary[0]+StructureOrigin[0],MetalBoundary[1]+StructureOrigin[1], boundaryRect=self.transformRectangle(boundaryRect,structureuVector,structurevVector)
MetalBoundary[2]+StructureOrigin[0],MetalBoundary[3]+StructureOrigin[1]] boundaryRect=[boundaryRect[0]+structureOrigin[0],boundaryRect[1]+structureOrigin[1],
boundaryRect[2]+structureOrigin[0],boundaryRect[3]+structureOrigin[1]]
if self.labelInRectangle(coordinates,MetalBoundary): if self.labelInRectangle(coordinates,boundaryRect):
boundaries.append(MetalBoundary) boundaries.append(boundaryRect)
return boundaries return boundaries
@ -829,7 +836,7 @@ class VlsiLayout:
def labelInRectangle(self,coordinate,rectangle): def labelInRectangle(self,coordinate,rectangle):
""" """
Checks if a coordinate is within a given rectangle. Checks if a coordinate is within a given rectangle. Rectangle is [leftx, bottomy, rightx, topy].
""" """
coordinate_In_Rectangle_x_range=(coordinate[0]>=int(rectangle[0]))&(coordinate[0]<=int(rectangle[2])) coordinate_In_Rectangle_x_range=(coordinate[0]>=int(rectangle[0]))&(coordinate[0]<=int(rectangle[2]))
coordinate_In_Rectangle_y_range=(coordinate[1]>=int(rectangle[1]))&(coordinate[1]<=int(rectangle[3])) coordinate_In_Rectangle_y_range=(coordinate[1]>=int(rectangle[1]))&(coordinate[1]<=int(rectangle[3]))

86
compiler/gen_stimulus.py Executable file
View File

@ -0,0 +1,86 @@
#!/usr/bin/env python2.7
"""
This script will generate a stimulus file for a given period, load, and slew input
for the given dimension SRAM. It is useful for debugging after an SRAM has been
created without re-running the entire process. Right now, it assumes the nominal
corner, but should probably be extended.
"""
import sys,os
import datetime
import re
import importlib
from globals import *
(OPTS, args) = parse_args()
# Override the usage
USAGE = "Usage: {} [options] <config file> <period in ns> <load in fF> <slew in ns>\nUse -h for help.\n".format(__file__)
# Check that we are left with a single configuration file as argument.
if len(args) != 4:
print(USAGE)
sys.exit(2)
# We need to get the:
# config file
config_file = args[0]
# period
period = float(args[1])
# load
load = float(args[2])
# slew
slew = float(args[3])
# These depend on arguments, so don't load them until now.
import debug
init_openram(config_file=config_file, is_unit_test=False)
OPTS.check_lvsdrc = False
# Put the temp output in the output path since it is what we want to generate!
old_openram_temp = OPTS.openram_temp
OPTS.openram_temp = OPTS.output_path
import sram
class fake_sram(sram.sram):
""" This is an SRAM that doesn't actually create itself, just computes
the sizes. """
def __init__(self, word_size, num_words, num_banks, name):
self.name = name
self.word_size = word_size
self.num_words = num_words
self.num_banks = num_banks
c = reload(__import__(OPTS.bitcell))
self.mod_bitcell = getattr(c, OPTS.bitcell)
self.bitcell = self.mod_bitcell()
# to get the row, col, etc.
self.compute_sizes()
sram = fake_sram(OPTS.word_size, OPTS.num_words, OPTS.num_banks, OPTS.output_name)
sp_file = OPTS.output_path+OPTS.output_name + ".sp"
from characterizer import delay
import tech
# Set up the delay and set to the nominal corner
d = delay.delay(sram, sp_file, ("TT", tech.spice["nom_supply_voltage"], tech.spice["nom_temperature"]))
# Set the period
d.period = period
# Set the load of outputs and slew of inputs
d.set_load_slew(load,slew)
# Set the probe address/bit
probe_address = "1" * sram.addr_size
probe_data = sram.word_size - 1
d.set_probe(probe_address, probe_data)
d.write_delay_stimulus()
# Output info about this run
report_status()
print("Output files are:\n{0}stim.sp\n{0}sram.sp\n{0}reduced.sp".format(OPTS.output_path))
OPTS.openram_temp = old_openram_temp
# Delete temp files, remove the dir, etc.
end_openram()

3
compiler/globals.py
View File

@ -167,6 +167,8 @@ def read_config(config_file, is_unit_test=True):
if not OPTS.output_path.endswith('/'): if not OPTS.output_path.endswith('/'):
OPTS.output_path += "/" OPTS.output_path += "/"
if not OPTS.output_path.startswith('/'):
OPTS.output_path = os.getcwd() + "/" + OPTS.output_path
debug.info(1, "Output saved in " + OPTS.output_path) debug.info(1, "Output saved in " + OPTS.output_path)
OPTS.is_unit_test=is_unit_test OPTS.is_unit_test=is_unit_test
@ -321,7 +323,6 @@ def report_status():
if not OPTS.tech_name: if not OPTS.tech_name:
debug.error("Tech name must be specified in config file.") debug.error("Tech name must be specified in config file.")
print("Output files are " + OPTS.output_name + ".(sp|gds|v|lib|lef)")
print("Technology: {0}".format(OPTS.tech_name)) print("Technology: {0}".format(OPTS.tech_name))
print("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size, print("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
OPTS.num_words, OPTS.num_words,

7
compiler/modules/control_logic.py
View File

@ -69,9 +69,10 @@ class control_logic(design.design):
c = reload(__import__(OPTS.replica_bitline)) c = reload(__import__(OPTS.replica_bitline))
replica_bitline = getattr(c, OPTS.replica_bitline) replica_bitline = getattr(c, OPTS.replica_bitline)
# FIXME: These should be tuned according to the size! # FIXME: These should be tuned according to the size!
FO4_stages = 8 delay_stages = 4 # This should be even so that the delay line is inverting!
bitcell_loads = int(math.ceil(self.num_rows / 10.0)) delay_fanout = 3
self.replica_bitline = replica_bitline(FO4_stages, bitcell_loads) bitcell_loads = int(math.ceil(self.num_rows / 5.0))
self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads)
self.add_mod(self.replica_bitline) self.add_mod(self.replica_bitline)

3
compiler/modules/delay_chain.py
View File

@ -20,6 +20,9 @@ class delay_chain(design.design):
# and there should be functions to get # and there should be functions to get
# area efficient inverter stage list # area efficient inverter stage list
for f in fanout_list:
debug.check(f>0,"Must have non-zero fanouts for each stage.")
# number of inverters including any fanout loads. # number of inverters including any fanout loads.
self.fanout_list = fanout_list self.fanout_list = fanout_list
self.num_inverters = 1 + sum(fanout_list) self.num_inverters = 1 + sum(fanout_list)

29
compiler/modules/dff.py Normal file
View File

@ -0,0 +1,29 @@
import globals
import design
from math import log
import design
from tech import GDS,layer
import utils
class dff(design.design):
"""
Memory address flip-flop
"""
pin_names = ["d", "q", "clk", "vdd", "gnd"]
(width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"], layer["boundary"])
def __init__(self, name="dff"):
design.design.__init__(self, name)
self.width = dff.width
self.height = dff.height
self.pin_map = dff.pin_map
def analytical_delay(self, slew, load = 0.0):
# dont know how to calculate this now, use constant in tech file
from tech import spice
result = self.return_delay(spice["dff_delay"], spice["dff_slew"])
return result

141
compiler/modules/dff_array.py Normal file
View File

@ -0,0 +1,141 @@
import debug
import design
from tech import drc
from math import log
from vector import vector
from globals import OPTS
class dff_array(design.design):
"""
This is a simple row (or multiple rows) of flops.
Unlike the data flops, these are never spaced out.
"""
def __init__(self, rows, columns, name=""):
self.rows = rows
self.columns = columns
if name=="":
name = "dff_array_{0}x{1}".format(rows, columns)
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
c = reload(__import__(OPTS.dff))
self.mod_dff = getattr(c, OPTS.dff)
self.ms = self.mod_dff("dff")
self.add_mod(self.ms)
self.width = self.columns * self.ms.width
self.height = self.rows * self.ms.height
self.create_layout()
def create_layout(self):
self.add_pins()
self.create_dff_array()
self.add_layout_pins()
self.DRC_LVS()
def add_pins(self):
for row in range(self.rows):
for col in range(self.columns):
self.add_pin("din[{0}][{1}]".format(row,col))
for row in range(self.rows):
for col in range(self.columns):
self.add_pin("dout[{0}][{1}]".format(row,col))
#self.add_pin("dout_bar[{0}]".format(i))
self.add_pin("clk")
self.add_pin("vdd")
self.add_pin("gnd")
def create_dff_array(self):
self.dff_insts={}
for y in range(self.rows):
for x in range(self.columns):
name = "Xdff_r{0}_c{1}".format(y,x)
if (y % 2 == 0):
base = vector(x*self.ms.width,y*self.ms.height)
mirror = "R0"
else:
base = vector(x*self.ms.width,(y+1)*self.ms.height)
mirror = "MX"
self.dff_insts[x,y]=self.add_inst(name=name,
mod=self.ms,
offset=base,
mirror=mirror)
self.connect_inst(["din[{0}][{1}]".format(x,y),
"dout[{0}][{1}]".format(x,y),
"clk",
"vdd",
"gnd"])
def add_layout_pins(self):
for y in range(self.rows):
# Continous vdd rail along with label.
vdd_pin=self.dff_insts[0,y].get_pin("vdd")
self.add_layout_pin(text="vdd",
layer="metal1",
offset=vdd_pin.ll(),
width=self.width,
height=self.m1_width)
# Continous gnd rail along with label.
gnd_pin=self.dff_insts[0,y].get_pin("gnd")
self.add_layout_pin(text="gnd",
layer="metal1",
offset=gnd_pin.ll(),
width=self.width,
height=self.m1_width)
for y in range(self.rows):
for x in range(self.columns):
din_pin = self.dff_insts[x,y].get_pin("d")
debug.check(din_pin.layer=="metal2","DFF d pin not on metal2")
self.add_layout_pin(text="din[{0}][{1}]".format(x,y),
layer=din_pin.layer,
offset=din_pin.ll(),
width=din_pin.width(),
height=din_pin.height())
dout_pin = self.dff_insts[x,y].get_pin("q")
debug.check(dout_pin.layer=="metal2","DFF q pin not on metal2")
self.add_layout_pin(text="dout[{0}][{1}]".format(x,y),
layer=dout_pin.layer,
offset=dout_pin.ll(),
width=dout_pin.width(),
height=dout_pin.height())
# Create vertical spines to a single horizontal rail
clk_pin = self.dff_insts[0,0].get_pin("clk")
debug.check(clk_pin.layer=="metal2","DFF clk pin not on metal2")
if self.columns==1:
self.add_layout_pin(text="clk",
layer="metal2",
offset=clk_pin.ll().scale(1,0),
width=self.m2_width,
height=self.height)
else:
self.add_layout_pin(text="clk",
layer="metal3",
offset=clk_pin.ll().scale(0,1),
width=self.width,
height=self.m3_width)
for x in range(self.columns):
clk_pin = self.dff_insts[x,0].get_pin("clk")
# Make a vertical strip for each column
self.add_layout_pin(text="clk",
layer="metal2",
offset=clk_pin.ll().scale(1,0),
width=self.m2_width,
height=self.height)
# Drop a via to the M3 pin
self.add_via_center(layers=("metal2","via2","metal3"),
offset=clk_pin.center())
def analytical_delay(self, slew, load=0.0):
return self.ms.analytical_delay(slew=slew, load=load)

9
compiler/modules/replica_bitline.py
View File

@ -11,11 +11,11 @@ from globals import OPTS
class replica_bitline(design.design): class replica_bitline(design.design):
""" """
Generate a module that simulates the delay of control logic Generate a module that simulates the delay of control logic
and bit line charging. Stages is the depth of the FO4 delay and bit line charging. Stages is the depth of the delay
line and rows is the height of the replica bit loads. line and rows is the height of the replica bit loads.
""" """
def __init__(self, FO4_stages, bitcell_loads, name="replica_bitline"): def __init__(self, delay_stages, delay_fanout, bitcell_loads, name="replica_bitline"):
design.design.__init__(self, name) design.design.__init__(self, name)
g = reload(__import__(OPTS.delay_chain)) g = reload(__import__(OPTS.delay_chain))
@ -30,7 +30,8 @@ class replica_bitline(design.design):
for pin in ["en", "out", "vdd", "gnd"]: for pin in ["en", "out", "vdd", "gnd"]:
self.add_pin(pin) self.add_pin(pin)
self.bitcell_loads = bitcell_loads self.bitcell_loads = bitcell_loads
self.FO4_stages = FO4_stages self.delay_stages = delay_stages
self.delay_fanout = delay_fanout
self.create_modules() self.create_modules()
self.calculate_module_offsets() self.calculate_module_offsets()
@ -83,7 +84,7 @@ class replica_bitline(design.design):
self.add_mod(self.rbl) self.add_mod(self.rbl)
# FIXME: The FO and depth of this should be tuned # FIXME: The FO and depth of this should be tuned
self.delay_chain = self.mod_delay_chain([4]*self.FO4_stages) self.delay_chain = self.mod_delay_chain([self.delay_fanout]*self.delay_stages)
self.add_mod(self.delay_chain) self.add_mod(self.delay_chain)
self.inv = pinv() self.inv = pinv()

2
compiler/openram.py
View File

@ -40,6 +40,8 @@ report_status()
import verify import verify
import sram import sram
print("Output files are " + OPTS.output_name + ".(sp|gds|v|lib|lef)")
# Keep track of running stats # Keep track of running stats
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
print_time("Start",start_time) print_time("Start",start_time)

2
compiler/options.py
View File

@ -58,6 +58,8 @@ class options(optparse.Values):
decoder = "hierarchical_decoder" decoder = "hierarchical_decoder"
ms_flop = "ms_flop" ms_flop = "ms_flop"
ms_flop_array = "ms_flop_array" ms_flop_array = "ms_flop_array"
dff = "dff"
dff_array = "dff_array"
control_logic = "control_logic" control_logic = "control_logic"
bitcell_array = "bitcell_array" bitcell_array = "bitcell_array"
sense_amp = "sense_amp" sense_amp = "sense_amp"

2
compiler/tests/00_code_format_check_test.py
View File

@ -35,6 +35,8 @@ class code_format_test(openram_test):
continue continue
if re.search("openram.py$", code): if re.search("openram.py$", code):
continue continue
if re.search("gen_stimulus.py$", code):
continue
errors += check_print_output(code) errors += check_print_output(code)
# fails if there are any tabs in any files # fails if there are any tabs in any files

44
compiler/tests/11_dff_array_test.py Normal file
View File

@ -0,0 +1,44 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on a dff_array.
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class dff_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import dff_array
debug.info(2, "Testing dff_array for 3x3")
a = dff_array.dff_array(rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 1x3")
a = dff_array.dff_array(rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 3x1")
a = dff_array.dff_array(rows=3, columns=1)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()

5
compiler/tests/14_replica_bitline_test.py
View File

@ -22,15 +22,16 @@ class replica_bitline_test(openram_test):
import replica_bitline import replica_bitline
stages=4 stages=4
fanout=4
rows=13 rows=13
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,rows) a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a) self.local_check(a)
stages=8 stages=8
rows=100 rows=100
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,rows) a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a) self.local_check(a)
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True

38
compiler/tests/21_hspice_delay_test.py
View File

@ -51,25 +51,27 @@ class timing_sram_test(openram_test):
data = d.analyze(probe_address, probe_data,slews,loads) data = d.analyze(probe_address, probe_data,slews,loads)
#print data #print data
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'read1_power': 0.0356004, golden_data = {'leakage_power': 0.0006964536000000001,
'read0_power': 0.0364339, 'delay_lh': [0.0573055],
'write0_power': 0.0262249, 'read0_power': [0.0337812],
'delay1': [0.0572987], 'read1_power': [0.032946500000000004],
'delay0': [0.0705677], 'write1_power': [0.0361529],
'min_period': 0.41, 'write0_power': [0.026179099999999997],
'write1_power': 0.038824700000000004, 'slew_hl': [0.0285185],
'slew0': [0.028478], 'min_period': 0.205,
'slew1': [0.0190058]} 'delay_hl': [0.070554],
'slew_lh': [0.0190073]}
elif OPTS.tech_name == "scn3me_subm": elif OPTS.tech_name == "scn3me_subm":
golden_data = {'read1_power': 10.3442, golden_data = {'leakage_power': 0.0004004581,
'read0_power': 10.5159, 'delay_lh': [0.6538954],
'write0_power': 6.9292, 'read0_power': [9.7622],
'delay1': [0.6536728], 'read1_power': [9.589],
'delay0': [0.9019465999999999], 'write1_power': [10.2578],
'min_period': 4.531, 'write0_power': [6.928400000000001],
'write1_power': 11.3108, 'slew_hl': [0.8321625],
'slew0': [0.8320245], 'min_period': 2.344,
'slew1': [0.5897582]} 'delay_hl': [0.9019090999999999],
'slew_lh': [0.5896232]}
else: else:
self.assertTrue(False) # other techs fail self.assertTrue(False) # other techs fail
# Check if no too many or too few results # Check if no too many or too few results

38
compiler/tests/21_ngspice_delay_test.py
View File

@ -49,25 +49,27 @@ class timing_sram_test(openram_test):
data = d.analyze(probe_address, probe_data,slews,loads) data = d.analyze(probe_address, probe_data,slews,loads)
#print data #print data
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'read1_power': 0.03308298, golden_data = {'leakage_power': 0.0007348262,
'read0_power': 0.03866541, 'delay_lh': [0.05799613],
'write0_power': 0.02695139, 'read0_power': [0.0384102],
'delay1': [0.05840294000000001], 'read1_power': [0.03279848],
'delay0': [0.40787249999999997], 'write1_power': [0.03693655],
'min_period': 0.781, 'write0_power': [0.02717752],
'write1_power': 0.037257830000000006, 'slew_hl': [0.03607912],
'slew0': [0.035826199999999996], 'min_period': 0.742,
'slew1': [0.02059459]} 'delay_hl': [0.3929995],
'slew_lh': [0.02160862]}
elif OPTS.tech_name == "scn3me_subm": elif OPTS.tech_name == "scn3me_subm":
golden_data = {'read1_power': 10.31395, golden_data = {'leakage_power': 0.00142014,
'read0_power': 10.0321, 'delay_lh': [0.8018421],
'write0_power': 6.072756, 'read0_power': [11.44908],
'delay1': [1.042564], 'read1_power': [11.416549999999999],
'delay0': [1.412224], 'write1_power': [11.718020000000001],
'min_period': 4.688, 'write0_power': [8.250219],
'write1_power': 10.53758, 'slew_hl': [0.8273725],
'slew0': [1.355812], 'min_period': 2.734,
'slew1': [1.03401]} 'delay_hl': [1.085861],
'slew_lh': [0.5730144]}
else: else:
self.assertTrue(False) # other techs fail self.assertTrue(False) # other techs fail

8
compiler/tests/21_ngspice_setuphold_test.py
View File

@ -40,10 +40,10 @@ class timing_setup_test(openram_test):
'hold_times_HL': [-0.003662109], 'hold_times_HL': [-0.003662109],
'setup_times_HL': [0.008544922]} 'setup_times_HL': [0.008544922]}
elif OPTS.tech_name == "scn3me_subm": elif OPTS.tech_name == "scn3me_subm":
golden_data = {'setup_times_LH': [0.1855469], golden_data = {'setup_times_LH': [0.07568359],
'hold_times_LH': [-0.009765625], 'hold_times_LH': [0.008544922],
'hold_times_HL': [-0.15625], 'hold_times_HL': [-0.05859374999999999],
'setup_times_HL': [0.12451169999999999]} 'setup_times_HL': [0.03295898]}
else: else:
self.assertTrue(False) # other techs fail self.assertTrue(False) # other techs fail

12
compiler/tests/22_sram_func_test.py
View File

@ -29,9 +29,9 @@ class sram_func_test(openram_test):
import sram import sram
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.word_size, s = sram.sram(word_size=1,
num_words=OPTS.num_words, num_words=16,
num_banks=OPTS.num_banks, num_banks=1,
name="sram_func_test") name="sram_func_test")
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True
@ -49,9 +49,9 @@ class sram_func_test(openram_test):
# This will exit if it doesn't find a feasible period # This will exit if it doesn't find a feasible period
import tech import tech
load = tech.spice["msflop_in_cap"]*4 d.load = tech.spice["msflop_in_cap"]*4
slew = tech.spice["rise_time"]*2 d.slew = tech.spice["rise_time"]*2
feasible_period = d.find_feasible_period(load,slew) feasible_period = d.find_feasible_period()
os.remove(tempspice) os.remove(tempspice)
OPTS.analytical_delay = True OPTS.analytical_delay = True

175
compiler/tests/golden/sram_2_16_1_freepdk45.lef
View File

@ -7,11 +7,11 @@ UNITS
END UNITS END UNITS
SITE MacroSite SITE MacroSite
CLASS Core ; CLASS Core ;
SIZE 21695.0 by 42337.5 ; SIZE 24385.0 by 42337.5 ;
END MacroSite END MacroSite
MACRO sram_2_16_1_freepdk45 MACRO sram_2_16_1_freepdk45
CLASS BLOCK ; CLASS BLOCK ;
SIZE 21695.0 BY 42337.5 ; SIZE 24385.0 BY 42337.5 ;
SYMMETRY X Y R90 ; SYMMETRY X Y R90 ;
SITE MacroSite ; SITE MacroSite ;
PIN DATA[0] PIN DATA[0]
@ -4165,12 +4165,15 @@ MACRO sram_2_16_1_freepdk45
RECT 750.0 30905.0 685.0 30970.0 ; RECT 750.0 30905.0 685.0 30970.0 ;
RECT 32.5 30615.0 -32.5 31175.0 ; RECT 32.5 30615.0 -32.5 31175.0 ;
RECT 1377.5 30615.0 1312.5 31175.0 ; RECT 1377.5 30615.0 1312.5 31175.0 ;
RECT 1377.5 39337.5 1312.5 36955.0 ; RECT 1377.5 38217.5 1312.5 39645.0 ;
RECT 1312.5 33907.5 1025.0 33972.5 ; RECT 1312.5 33907.5 1025.0 33972.5 ;
RECT 1312.5 36317.5 1025.0 36382.5 ; RECT 1312.5 36317.5 1025.0 36382.5 ;
RECT 1312.5 36597.5 1025.0 36662.5 ;
RECT 1312.5 39007.5 1025.0 39072.5 ;
RECT 1377.5 31862.5 935.0 31927.5 ; RECT 1377.5 31862.5 935.0 31927.5 ;
RECT 935.0 31862.5 230.0 31927.5 ; RECT 935.0 31862.5 230.0 31927.5 ;
RECT 20.0 35112.5 935.0 35177.5 ; RECT 20.0 35112.5 935.0 35177.5 ;
RECT 20.0 37802.5 935.0 37867.5 ;
RECT 20.0 32422.5 935.0 32487.5 ; RECT 20.0 32422.5 935.0 32487.5 ;
RECT 2005.0 33435.0 1940.0 34135.0 ; RECT 2005.0 33435.0 1940.0 34135.0 ;
RECT 2005.0 33627.5 1940.0 33692.5 ; RECT 2005.0 33627.5 1940.0 33692.5 ;
@ -4210,11 +4213,11 @@ MACRO sram_2_16_1_freepdk45
RECT 2330.0 33497.5 2465.0 33562.5 ; RECT 2330.0 33497.5 2465.0 33562.5 ;
RECT 2330.0 33497.5 2465.0 33562.5 ; RECT 2330.0 33497.5 2465.0 33562.5 ;
RECT 2330.0 33307.5 2465.0 33372.5 ; RECT 2330.0 33307.5 2465.0 33372.5 ;
RECT 1312.5 39272.5 1377.5 39337.5 ; RECT 1312.5 38152.5 1377.5 38217.5 ;
RECT 4002.5 39272.5 4067.5 39337.5 ; RECT 4002.5 38152.5 4067.5 38217.5 ;
RECT 1312.5 39175.0 1377.5 39305.0 ; RECT 1312.5 38055.0 1377.5 38185.0 ;
RECT 1345.0 39272.5 4035.0 39337.5 ; RECT 1345.0 38152.5 4035.0 38217.5 ;
RECT 4002.5 39175.0 4067.5 39305.0 ; RECT 4002.5 38055.0 4067.5 38185.0 ;
RECT 2875.0 34562.5 2690.0 34627.5 ; RECT 2875.0 34562.5 2690.0 34627.5 ;
RECT 4035.0 34562.5 3850.0 34627.5 ; RECT 4035.0 34562.5 3850.0 34627.5 ;
RECT 3917.5 34202.5 4067.5 34267.5 ; RECT 3917.5 34202.5 4067.5 34267.5 ;
@ -4361,90 +4364,6 @@ MACRO sram_2_16_1_freepdk45
RECT 2722.5 37495.0 2657.5 38055.0 ; RECT 2722.5 37495.0 2657.5 38055.0 ;
RECT 4067.5 37495.0 4002.5 38055.0 ; RECT 4067.5 37495.0 4002.5 38055.0 ;
RECT 3340.0 37620.0 3475.0 37685.0 ; RECT 3340.0 37620.0 3475.0 37685.0 ;
RECT 2875.0 38482.5 2690.0 38547.5 ;
RECT 4035.0 38482.5 3850.0 38547.5 ;
RECT 3917.5 38122.5 4067.5 38187.5 ;
RECT 3032.5 38122.5 2657.5 38187.5 ;
RECT 3917.5 38312.5 3032.5 38377.5 ;
RECT 3032.5 38122.5 2897.5 38187.5 ;
RECT 3032.5 38312.5 2897.5 38377.5 ;
RECT 3032.5 38312.5 2897.5 38377.5 ;
RECT 3032.5 38122.5 2897.5 38187.5 ;
RECT 3917.5 38122.5 3782.5 38187.5 ;
RECT 3917.5 38312.5 3782.5 38377.5 ;
RECT 3917.5 38312.5 3782.5 38377.5 ;
RECT 3917.5 38122.5 3782.5 38187.5 ;
RECT 2942.5 38482.5 2807.5 38547.5 ;
RECT 3917.5 38482.5 3782.5 38547.5 ;
RECT 3475.0 38180.0 3340.0 38245.0 ;
RECT 3475.0 38180.0 3340.0 38245.0 ;
RECT 3440.0 38345.0 3375.0 38410.0 ;
RECT 2722.5 38055.0 2657.5 38615.0 ;
RECT 4067.5 38055.0 4002.5 38615.0 ;
RECT 3340.0 38180.0 3475.0 38245.0 ;
RECT 2875.0 39042.5 2690.0 39107.5 ;
RECT 4035.0 39042.5 3850.0 39107.5 ;
RECT 3917.5 38682.5 4067.5 38747.5 ;
RECT 3032.5 38682.5 2657.5 38747.5 ;
RECT 3917.5 38872.5 3032.5 38937.5 ;
RECT 3032.5 38682.5 2897.5 38747.5 ;
RECT 3032.5 38872.5 2897.5 38937.5 ;
RECT 3032.5 38872.5 2897.5 38937.5 ;
RECT 3032.5 38682.5 2897.5 38747.5 ;
RECT 3917.5 38682.5 3782.5 38747.5 ;
RECT 3917.5 38872.5 3782.5 38937.5 ;
RECT 3917.5 38872.5 3782.5 38937.5 ;
RECT 3917.5 38682.5 3782.5 38747.5 ;
RECT 2942.5 39042.5 2807.5 39107.5 ;
RECT 3917.5 39042.5 3782.5 39107.5 ;
RECT 3475.0 38740.0 3340.0 38805.0 ;
RECT 3475.0 38740.0 3340.0 38805.0 ;
RECT 3440.0 38905.0 3375.0 38970.0 ;
RECT 2722.5 38615.0 2657.5 39175.0 ;
RECT 4067.5 38615.0 4002.5 39175.0 ;
RECT 3340.0 38740.0 3475.0 38805.0 ;
RECT 2505.0 38187.5 2690.0 38122.5 ;
RECT 1345.0 38187.5 1530.0 38122.5 ;
RECT 1462.5 38547.5 1312.5 38482.5 ;
RECT 2347.5 38547.5 2722.5 38482.5 ;
RECT 1462.5 38357.5 2347.5 38292.5 ;
RECT 2347.5 38547.5 2482.5 38482.5 ;
RECT 2347.5 38357.5 2482.5 38292.5 ;
RECT 2347.5 38357.5 2482.5 38292.5 ;
RECT 2347.5 38547.5 2482.5 38482.5 ;
RECT 1462.5 38547.5 1597.5 38482.5 ;
RECT 1462.5 38357.5 1597.5 38292.5 ;
RECT 1462.5 38357.5 1597.5 38292.5 ;
RECT 1462.5 38547.5 1597.5 38482.5 ;
RECT 2437.5 38187.5 2572.5 38122.5 ;
RECT 1462.5 38187.5 1597.5 38122.5 ;
RECT 1905.0 38490.0 2040.0 38425.0 ;
RECT 1905.0 38490.0 2040.0 38425.0 ;
RECT 1940.0 38325.0 2005.0 38260.0 ;
RECT 2657.5 38615.0 2722.5 38055.0 ;
RECT 1312.5 38615.0 1377.5 38055.0 ;
RECT 1905.0 38425.0 2040.0 38490.0 ;
RECT 2505.0 37627.5 2690.0 37562.5 ;
RECT 1345.0 37627.5 1530.0 37562.5 ;
RECT 1462.5 37987.5 1312.5 37922.5 ;
RECT 2347.5 37987.5 2722.5 37922.5 ;
RECT 1462.5 37797.5 2347.5 37732.5 ;
RECT 2347.5 37987.5 2482.5 37922.5 ;
RECT 2347.5 37797.5 2482.5 37732.5 ;
RECT 2347.5 37797.5 2482.5 37732.5 ;
RECT 2347.5 37987.5 2482.5 37922.5 ;
RECT 1462.5 37987.5 1597.5 37922.5 ;
RECT 1462.5 37797.5 1597.5 37732.5 ;
RECT 1462.5 37797.5 1597.5 37732.5 ;
RECT 1462.5 37987.5 1597.5 37922.5 ;
RECT 2437.5 37627.5 2572.5 37562.5 ;
RECT 1462.5 37627.5 1597.5 37562.5 ;
RECT 1905.0 37930.0 2040.0 37865.0 ;
RECT 1905.0 37930.0 2040.0 37865.0 ;
RECT 1940.0 37765.0 2005.0 37700.0 ;
RECT 2657.5 38055.0 2722.5 37495.0 ;
RECT 1312.5 38055.0 1377.5 37495.0 ;
RECT 1905.0 37865.0 2040.0 37930.0 ;
RECT 2505.0 37067.5 2690.0 37002.5 ; RECT 2505.0 37067.5 2690.0 37002.5 ;
RECT 1345.0 37067.5 1530.0 37002.5 ; RECT 1345.0 37067.5 1530.0 37002.5 ;
RECT 1462.5 37427.5 1312.5 37362.5 ; RECT 1462.5 37427.5 1312.5 37362.5 ;
@ -4572,24 +4491,32 @@ MACRO sram_2_16_1_freepdk45
RECT 1312.5 34695.0 1377.5 34135.0 ; RECT 1312.5 34695.0 1377.5 34135.0 ;
RECT 1905.0 34505.0 2040.0 34570.0 ; RECT 1905.0 34505.0 2040.0 34570.0 ;
RECT 3340.0 34425.0 3475.0 34490.0 ; RECT 3340.0 34425.0 3475.0 34490.0 ;
RECT 3340.0 36665.0 3475.0 36730.0 ; RECT 3340.0 36105.0 3475.0 36170.0 ;
RECT 3340.0 38905.0 3475.0 38970.0 ; RECT 3340.0 37785.0 3475.0 37850.0 ;
RECT 1905.0 36580.0 2040.0 36645.0 ; RECT 1905.0 36020.0 2040.0 36085.0 ;
RECT 3340.0 34260.0 3475.0 34325.0 ; RECT 3340.0 34260.0 3475.0 34325.0 ;
RECT 1940.0 34135.0 2005.0 34340.0 ; RECT 1940.0 34135.0 2005.0 34340.0 ;
RECT 2657.5 34135.0 2722.5 39175.0 ; RECT 2657.5 34135.0 2722.5 38055.0 ;
RECT 1312.5 34135.0 1377.5 39175.0 ; RECT 1312.5 34135.0 1377.5 38055.0 ;
RECT 4002.5 34135.0 4067.5 39175.0 ; RECT 4002.5 34135.0 4067.5 38055.0 ;
RECT 935.0 33800.0 225.0 32455.0 ; RECT 935.0 33800.0 225.0 32455.0 ;
RECT 935.0 33800.0 230.0 35145.0 ; RECT 935.0 33800.0 230.0 35145.0 ;
RECT 935.0 36490.0 230.0 35145.0 ; RECT 935.0 36490.0 230.0 35145.0 ;
RECT 935.0 36490.0 230.0 37835.0 ;
RECT 935.0 39180.0 230.0 37835.0 ;
RECT 1025.0 33907.5 140.0 33972.5 ; RECT 1025.0 33907.5 140.0 33972.5 ;
RECT 1025.0 36317.5 140.0 36382.5 ; RECT 1025.0 36317.5 140.0 36382.5 ;
RECT 1025.0 36597.5 140.0 36662.5 ;
RECT 1025.0 39007.5 140.0 39072.5 ;
RECT 1025.0 35112.5 140.0 35177.5 ; RECT 1025.0 35112.5 140.0 35177.5 ;
RECT 1025.0 37802.5 140.0 37867.5 ;
RECT 1025.0 33767.5 140.0 33832.5 ; RECT 1025.0 33767.5 140.0 33832.5 ;
RECT 1025.0 36457.5 140.0 36522.5 ; RECT 1025.0 36457.5 140.0 36522.5 ;
RECT 1025.0 39147.5 140.0 39212.5 ;
RECT 1345.0 33872.5 1280.0 34007.5 ; RECT 1345.0 33872.5 1280.0 34007.5 ;
RECT 1345.0 36282.5 1280.0 36417.5 ; RECT 1345.0 36282.5 1280.0 36417.5 ;
RECT 1345.0 36562.5 1280.0 36697.5 ;
RECT 1345.0 38972.5 1280.0 39107.5 ;
RECT 1342.5 34135.0 1277.5 34270.0 ; RECT 1342.5 34135.0 1277.5 34270.0 ;
RECT 1377.5 31760.0 1312.5 31895.0 ; RECT 1377.5 31760.0 1312.5 31895.0 ;
RECT 867.5 31862.5 1002.5 31927.5 ; RECT 867.5 31862.5 1002.5 31927.5 ;
@ -4600,7 +4527,7 @@ MACRO sram_2_16_1_freepdk45
RECT 682.5 32030.0 817.5 32095.0 ; RECT 682.5 32030.0 817.5 32095.0 ;
RECT 3475.0 31335.0 3410.0 34260.0 ; RECT 3475.0 31335.0 3410.0 34260.0 ;
RECT 2005.0 31335.0 1940.0 32100.0 ; RECT 2005.0 31335.0 1940.0 32100.0 ;
RECT 20.0 31335.0 -45.0 36577.5 ; RECT 20.0 31335.0 -45.0 39267.5 ;
RECT 2722.5 31335.0 2657.5 34135.0 ; RECT 2722.5 31335.0 2657.5 34135.0 ;
RECT 1377.5 31335.0 1312.5 31895.0 ; RECT 1377.5 31335.0 1312.5 31895.0 ;
RECT 4067.5 31335.0 4002.5 34135.0 ; RECT 4067.5 31335.0 4002.5 34135.0 ;
@ -5439,29 +5366,25 @@ MACRO sram_2_16_1_freepdk45
RECT 1610.0 26387.5 1540.0 26252.5 ; RECT 1610.0 26387.5 1540.0 26252.5 ;
RECT 2315.0 25737.5 2245.0 25602.5 ; RECT 2315.0 25737.5 2245.0 25602.5 ;
RECT 2315.0 26387.5 2245.0 26252.5 ; RECT 2315.0 26387.5 2245.0 26252.5 ;
RECT 1380.0 31895.0 1310.0 36955.0 ; RECT 1380.0 31895.0 1310.0 39645.0 ;
RECT 970.0 31895.0 900.0 36645.0 ; RECT 970.0 31895.0 900.0 39335.0 ;
RECT 265.0 31895.0 195.0 36645.0 ; RECT 265.0 31895.0 195.0 39335.0 ;
RECT 1207.5 32062.5 1137.5 32660.0 ; RECT 1207.5 32062.5 1137.5 32660.0 ;
RECT 785.0 32062.5 715.0 32342.5 ; RECT 785.0 32062.5 715.0 32342.5 ;
RECT 3372.5 34457.5 3442.5 34852.5 ; RECT 3372.5 34457.5 3442.5 34852.5 ;
RECT 3372.5 34852.5 3442.5 35412.5 ; RECT 3372.5 34852.5 3442.5 35412.5 ;
RECT 3372.5 35412.5 3442.5 35972.5 ; RECT 3372.5 35412.5 3442.5 35972.5 ;
RECT 3372.5 35972.5 3442.5 36532.5 ; RECT 3372.5 36137.5 3442.5 36532.5 ;
RECT 3372.5 36697.5 3442.5 37092.5 ; RECT 3372.5 36532.5 3442.5 37092.5 ;
RECT 3372.5 37092.5 3442.5 37652.5 ; RECT 3372.5 37092.5 3442.5 37652.5 ;
RECT 3372.5 37652.5 3442.5 38212.5 ; RECT 2655.0 37782.5 2725.0 37852.5 ;
RECT 3372.5 38212.5 3442.5 38772.5 ; RECT 2655.0 37302.5 2725.0 37372.5 ;
RECT 2655.0 38902.5 2725.0 38972.5 ; RECT 2690.0 37782.5 3407.5 37852.5 ;
RECT 2655.0 38422.5 2725.0 38492.5 ; RECT 2655.0 37337.5 2725.0 37817.5 ;
RECT 2690.0 38902.5 3407.5 38972.5 ; RECT 1972.5 37302.5 2690.0 37372.5 ;
RECT 2655.0 38457.5 2725.0 38937.5 ;
RECT 1972.5 38422.5 2690.0 38492.5 ;
RECT 1937.5 37897.5 2007.5 38457.5 ;
RECT 1937.5 37337.5 2007.5 37897.5 ;
RECT 1937.5 36777.5 2007.5 37337.5 ; RECT 1937.5 36777.5 2007.5 37337.5 ;
RECT 1937.5 36217.5 2007.5 36612.5 ; RECT 1937.5 36217.5 2007.5 36777.5 ;
RECT 1937.5 35657.5 2007.5 36217.5 ; RECT 1937.5 35657.5 2007.5 36052.5 ;
RECT 1937.5 35097.5 2007.5 35657.5 ; RECT 1937.5 35097.5 2007.5 35657.5 ;
RECT 1937.5 34537.5 2007.5 35097.5 ; RECT 1937.5 34537.5 2007.5 35097.5 ;
RECT 3340.0 34817.5 3475.0 34887.5 ; RECT 3340.0 34817.5 3475.0 34887.5 ;
@ -5470,10 +5393,6 @@ MACRO sram_2_16_1_freepdk45
RECT 3340.0 36497.5 3475.0 36567.5 ; RECT 3340.0 36497.5 3475.0 36567.5 ;
RECT 3340.0 37057.5 3475.0 37127.5 ; RECT 3340.0 37057.5 3475.0 37127.5 ;
RECT 3340.0 37617.5 3475.0 37687.5 ; RECT 3340.0 37617.5 3475.0 37687.5 ;
RECT 3340.0 38177.5 3475.0 38247.5 ;
RECT 3340.0 38737.5 3475.0 38807.5 ;
RECT 1905.0 38422.5 2040.0 38492.5 ;
RECT 1905.0 37862.5 2040.0 37932.5 ;
RECT 1905.0 37302.5 2040.0 37372.5 ; RECT 1905.0 37302.5 2040.0 37372.5 ;
RECT 1905.0 36742.5 2040.0 36812.5 ; RECT 1905.0 36742.5 2040.0 36812.5 ;
RECT 1905.0 36182.5 2040.0 36252.5 ; RECT 1905.0 36182.5 2040.0 36252.5 ;
@ -5481,18 +5400,22 @@ MACRO sram_2_16_1_freepdk45
RECT 1905.0 35062.5 2040.0 35132.5 ; RECT 1905.0 35062.5 2040.0 35132.5 ;
RECT 1905.0 34502.5 2040.0 34572.5 ; RECT 1905.0 34502.5 2040.0 34572.5 ;
RECT 3340.0 34422.5 3475.0 34492.5 ; RECT 3340.0 34422.5 3475.0 34492.5 ;
RECT 3340.0 36662.5 3475.0 36732.5 ; RECT 3340.0 36102.5 3475.0 36172.5 ;
RECT 3340.0 38902.5 3475.0 38972.5 ; RECT 3340.0 37782.5 3475.0 37852.5 ;
RECT 1905.0 36577.5 2040.0 36647.5 ; RECT 1905.0 36017.5 2040.0 36087.5 ;
RECT 935.0 33800.0 225.0 32455.0 ; RECT 935.0 33800.0 225.0 32455.0 ;
RECT 935.0 33800.0 230.0 35145.0 ; RECT 935.0 33800.0 230.0 35145.0 ;
RECT 935.0 36490.0 230.0 35145.0 ; RECT 935.0 36490.0 230.0 35145.0 ;
RECT 785.0 33700.0 715.0 36645.0 ; RECT 935.0 36490.0 230.0 37835.0 ;
RECT 450.0 33700.0 380.0 36645.0 ; RECT 935.0 39180.0 230.0 37835.0 ;
RECT 970.0 33700.0 900.0 36645.0 ; RECT 785.0 33700.0 715.0 39335.0 ;
RECT 265.0 33700.0 195.0 36645.0 ; RECT 450.0 33700.0 380.0 39335.0 ;
RECT 970.0 33700.0 900.0 39335.0 ;
RECT 265.0 33700.0 195.0 39335.0 ;
RECT 1347.5 33872.5 1277.5 34007.5 ; RECT 1347.5 33872.5 1277.5 34007.5 ;
RECT 1347.5 36282.5 1277.5 36417.5 ; RECT 1347.5 36282.5 1277.5 36417.5 ;
RECT 1347.5 36562.5 1277.5 36697.5 ;
RECT 1347.5 38972.5 1277.5 39107.5 ;
RECT 1345.0 34135.0 1275.0 34270.0 ; RECT 1345.0 34135.0 1275.0 34270.0 ;
RECT 1380.0 31760.0 1310.0 31895.0 ; RECT 1380.0 31760.0 1310.0 31895.0 ;
RECT 867.5 31860.0 1002.5 31930.0 ; RECT 867.5 31860.0 1002.5 31930.0 ;

84
compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C.lib → compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_freepdk45_TT_10V_25C_lib){ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup"; delay_model : "table_lookup";
time_unit : "1ns" ; time_unit : "1ns" ;
voltage_unit : "1v" ; voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
capacitive_load_unit(1 ,fF) ; capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ; leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ; pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){ operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ; voltage : 1.0 ;
temperature : 25; temperature : 25;
} }
@ -21,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ; slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ; slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ; default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ; default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ; default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
index_2("0.00125, 0.005, 0.04"); index_2("0.00125, 0.005, 0.04");
} }
default_operating_conditions : TT; default_operating_conditions : OC;
type (DATA){ type (DATA){
@ -74,12 +78,18 @@ cell (sram_2_16_1_freepdk45){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 918.5120625; area : 1032.3999375;
leakage_power () {
when : "CSb";
value : 0.00088149731;
}
cell_leakage_power : 0;
bus(DATA){ bus(DATA){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : inout;
max_capacitance : 1.6728; max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk"; three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_freepdk45){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0.042347092");
}
fall_power(scalar){
values("0.029908723");
}
}
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_freepdk45){
"-0.004, -0.004, -0.016"); "-0.004, -0.004, -0.016");
} }
} }
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0.054779642");
}
fall_power(scalar){
values("0.060081573");
}
}
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
@ -145,16 +137,16 @@ cell (sram_2_16_1_freepdk45){
"0.061, 0.062, 0.069"); "0.061, 0.062, 0.069");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.522, 0.523, 0.533",\ values("0.429, 0.43, 0.439",\
"0.523, 0.524, 0.533",\ "0.429, 0.431, 0.439",\
"0.528, 0.529, 0.539"); "0.435, 0.436, 0.446");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.013, 0.015, 0.026",\ values("0.013, 0.015, 0.026",\
"0.013, 0.015, 0.026",\ "0.013, 0.015, 0.026",\
"0.013, 0.015, 0.026"); "0.013, 0.015, 0.026");
} }
fall_transition(CELL_TABLE) { fall_transition(CELL_TABLE) {
values("0.029, 0.031, 0.044",\ values("0.029, 0.031, 0.044",\
"0.029, 0.031, 0.044",\ "0.029, 0.031, 0.044",\
"0.029, 0.031, 0.044"); "0.029, 0.031, 0.044");
@ -168,7 +160,6 @@ cell (sram_2_16_1_freepdk45){
direction : input; direction : input;
capacitance : 0.2091; capacitance : 0.2091;
max_transition : 0.04; max_transition : 0.04;
fanout_load : 1.000000;
pin(ADDR[3:0]){ pin(ADDR[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
@ -304,24 +295,51 @@ cell (sram_2_16_1_freepdk45){
clock : true; clock : true;
direction : input; direction : input;
capacitance : 0.2091; capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0173748762222");
}
fall_power(scalar){
values("0.0173748762222");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0261209913889");
}
fall_power(scalar){
values("0.0261209913889");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){ timing(){
timing_type :"min_pulse_width"; timing_type :"min_pulse_width";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("0.5275"); values("0.4295");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("0.5275"); values("0.4295");
} }
} }
timing(){ timing(){
timing_type :"minimum_period"; timing_type :"minimum_period";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("1.055"); values("0.859");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("1.055"); values("0.859");
} }
} }
} }

347
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib Normal file
View File

@ -0,0 +1,347 @@
library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.00125, 0.005, 0.04");
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 2;
bit_from : 0;
bit_to : 1;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 4;
bit_from : 0;
bit_to : 3;
}
cell (sram_2_16_1_freepdk45){
memory(){
type : ram;
address_width : 4;
word_width : 2;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 1032.3999375;
leakage_power () {
when : "CSb";
value : 0;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
memory_read(){
address : ADDR;
}
pin(DATA[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.123, 0.124, 0.133",\
"0.123, 0.124, 0.133",\
"0.123, 0.124, 0.133");
}
cell_fall(CELL_TABLE) {
values("0.123, 0.124, 0.133",\
"0.123, 0.124, 0.133",\
"0.123, 0.124, 0.133");
}
rise_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018");
}
fall_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018");
}
}
}
}
bus(ADDR){
bus_type : ADDR;
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
}
pin(CSb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("0.0");
}
fall_constraint(scalar) {
values("0.0");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("0.0");
}
fall_constraint(scalar) {
values("0.0");
}
}
}
}
}

84
compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_analytical.lib → compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_freepdk45_TT_10V_25C_lib){ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup"; delay_model : "table_lookup";
time_unit : "1ns" ; time_unit : "1ns" ;
voltage_unit : "1v" ; voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
capacitive_load_unit(1 ,fF) ; capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ; leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ; pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){ operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ; voltage : 1.0 ;
temperature : 25; temperature : 25;
} }
@ -21,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ; slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ; slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ; default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ; default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ; default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
index_2("0.00125, 0.005, 0.04"); index_2("0.00125, 0.005, 0.04");
} }
default_operating_conditions : TT; default_operating_conditions : OC;
type (DATA){ type (DATA){
@ -74,12 +78,18 @@ cell (sram_2_16_1_freepdk45){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 918.5120625; area : 1032.3999375;
leakage_power () {
when : "CSb";
value : 0.00088149731;
}
cell_leakage_power : 0;
bus(DATA){ bus(DATA){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : inout;
max_capacitance : 1.6728; max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk"; three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_freepdk45){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0.039115101");
}
fall_power(scalar){
values("0.026662611");
}
}
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_freepdk45){
"-0.004, -0.004, -0.016"); "-0.004, -0.004, -0.016");
} }
} }
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0.036300681");
}
fall_power(scalar){
values("0.041472985");
}
}
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
@ -145,16 +137,16 @@ cell (sram_2_16_1_freepdk45){
"0.06, 0.061, 0.067"); "0.06, 0.061, 0.067");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.519, 0.52, 0.529",\ values("0.425, 0.426, 0.436",\
"0.519, 0.52, 0.53",\ "0.426, 0.427, 0.436",\
"0.525, 0.526, 0.535"); "0.432, 0.433, 0.442");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.013, 0.014, 0.026",\ values("0.013, 0.014, 0.026",\
"0.013, 0.014, 0.026",\ "0.013, 0.014, 0.026",\
"0.013, 0.015, 0.026"); "0.013, 0.015, 0.026");
} }
fall_transition(CELL_TABLE) { fall_transition(CELL_TABLE) {
values("0.027, 0.029, 0.043",\ values("0.027, 0.029, 0.043",\
"0.027, 0.029, 0.043",\ "0.027, 0.029, 0.043",\
"0.027, 0.029, 0.043"); "0.027, 0.029, 0.043");
@ -168,7 +160,6 @@ cell (sram_2_16_1_freepdk45){
direction : input; direction : input;
capacitance : 0.2091; capacitance : 0.2091;
max_transition : 0.04; max_transition : 0.04;
fanout_load : 1.000000;
pin(ADDR[3:0]){ pin(ADDR[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
@ -304,24 +295,51 @@ cell (sram_2_16_1_freepdk45){
clock : true; clock : true;
direction : input; direction : input;
capacitance : 0.2091; capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0158174252672");
}
fall_power(scalar){
values("0.0158174252672");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0181396362394");
}
fall_power(scalar){
values("0.0181396362394");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){ timing(){
timing_type :"min_pulse_width"; timing_type :"min_pulse_width";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("0.5275"); values("0.4295");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("0.5275"); values("0.4295");
} }
} }
timing(){ timing(){
timing_type :"minimum_period"; timing_type :"minimum_period";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("1.055"); values("0.859");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("1.055"); values("0.859");
} }
} }
} }

174
compiler/tests/golden/sram_2_16_1_scn3me_subm.lef
View File

@ -7,11 +7,11 @@ UNITS
END UNITS END UNITS
SITE MacroSite SITE MacroSite
CLASS Core ; CLASS Core ;
SIZE 277800.0 by 440700.0 ; SIZE 305400.0 by 440700.0 ;
END MacroSite END MacroSite
MACRO sram_2_16_1_scn3me_subm MACRO sram_2_16_1_scn3me_subm
CLASS BLOCK ; CLASS BLOCK ;
SIZE 277800.0 BY 440700.0 ; SIZE 305400.0 BY 440700.0 ;
SYMMETRY X Y R90 ; SYMMETRY X Y R90 ;
SITE MacroSite ; SITE MacroSite ;
PIN DATA[0] PIN DATA[0]
@ -4105,12 +4105,15 @@ MACRO sram_2_16_1_scn3me_subm
RECT 16050.0 358350.0 15150.0 359250.0 ; RECT 16050.0 358350.0 15150.0 359250.0 ;
RECT 8850.0 353400.0 7950.0 363000.0 ; RECT 8850.0 353400.0 7950.0 363000.0 ;
RECT 22650.0 353400.0 21750.0 363000.0 ; RECT 22650.0 353400.0 21750.0 363000.0 ;
RECT 22650.0 499050.0 21750.0 430200.0 ; RECT 22650.0 479850.0 21750.0 457800.0 ;
RECT 21750.0 397050.0 17400.0 397950.0 ; RECT 21750.0 397050.0 17400.0 397950.0 ;
RECT 21750.0 420450.0 17400.0 421350.0 ; RECT 21750.0 420450.0 17400.0 421350.0 ;
RECT 21750.0 424650.0 17400.0 425550.0 ;
RECT 21750.0 448050.0 17400.0 448950.0 ;
RECT 22650.0 371550.0 16800.0 372450.0 ; RECT 22650.0 371550.0 16800.0 372450.0 ;
RECT 16800.0 371550.0 6600.0 372450.0 ; RECT 16800.0 371550.0 6600.0 372450.0 ;
RECT 4500.0 408600.0 16800.0 409500.0 ; RECT 4500.0 408600.0 16800.0 409500.0 ;
RECT 4500.0 436200.0 16800.0 437100.0 ;
RECT 4500.0 381000.0 16800.0 381900.0 ; RECT 4500.0 381000.0 16800.0 381900.0 ;
RECT 29250.0 397800.0 28350.0 410400.0 ; RECT 29250.0 397800.0 28350.0 410400.0 ;
RECT 29250.0 392850.0 28350.0 393750.0 ; RECT 29250.0 392850.0 28350.0 393750.0 ;
@ -4150,11 +4153,11 @@ MACRO sram_2_16_1_scn3me_subm
RECT 32550.0 398400.0 33750.0 399600.0 ; RECT 32550.0 398400.0 33750.0 399600.0 ;
RECT 32550.0 398400.0 33750.0 399600.0 ; RECT 32550.0 398400.0 33750.0 399600.0 ;
RECT 32550.0 396000.0 33750.0 397200.0 ; RECT 32550.0 396000.0 33750.0 397200.0 ;
RECT 21750.0 498150.0 22650.0 499050.0 ; RECT 21750.0 478950.0 22650.0 479850.0 ;
RECT 49350.0 498150.0 50250.0 499050.0 ; RECT 49350.0 478950.0 50250.0 479850.0 ;
RECT 21750.0 496800.0 22650.0 498600.0 ; RECT 21750.0 477600.0 22650.0 479400.0 ;
RECT 22200.0 498150.0 49800.0 499050.0 ; RECT 22200.0 478950.0 49800.0 479850.0 ;
RECT 49350.0 496800.0 50250.0 498600.0 ; RECT 49350.0 477600.0 50250.0 479400.0 ;
RECT 37950.0 417000.0 36000.0 418200.0 ; RECT 37950.0 417000.0 36000.0 418200.0 ;
RECT 49800.0 417000.0 47850.0 418200.0 ; RECT 49800.0 417000.0 47850.0 418200.0 ;
RECT 48450.0 412200.0 50250.0 413400.0 ; RECT 48450.0 412200.0 50250.0 413400.0 ;
@ -4301,90 +4304,6 @@ MACRO sram_2_16_1_scn3me_subm
RECT 36450.0 468000.0 35550.0 477600.0 ; RECT 36450.0 468000.0 35550.0 477600.0 ;
RECT 50250.0 468000.0 49350.0 477600.0 ; RECT 50250.0 468000.0 49350.0 477600.0 ;
RECT 42600.0 470400.0 43800.0 471600.0 ; RECT 42600.0 470400.0 43800.0 471600.0 ;
RECT 37950.0 484200.0 36000.0 485400.0 ;
RECT 49800.0 484200.0 47850.0 485400.0 ;
RECT 48450.0 479400.0 50250.0 480600.0 ;
RECT 39150.0 479400.0 35550.0 480600.0 ;
RECT 48450.0 482100.0 39150.0 483000.0 ;
RECT 39150.0 479400.0 37950.0 480600.0 ;
RECT 39150.0 481800.0 37950.0 483000.0 ;
RECT 39150.0 481800.0 37950.0 483000.0 ;
RECT 39150.0 479400.0 37950.0 480600.0 ;
RECT 48450.0 479400.0 47250.0 480600.0 ;
RECT 48450.0 481800.0 47250.0 483000.0 ;
RECT 48450.0 481800.0 47250.0 483000.0 ;
RECT 48450.0 479400.0 47250.0 480600.0 ;
RECT 38550.0 484200.0 37350.0 485400.0 ;
RECT 48450.0 484200.0 47250.0 485400.0 ;
RECT 43800.0 480000.0 42600.0 481200.0 ;
RECT 43800.0 480000.0 42600.0 481200.0 ;
RECT 43650.0 482550.0 42750.0 483450.0 ;
RECT 36450.0 477600.0 35550.0 487200.0 ;
RECT 50250.0 477600.0 49350.0 487200.0 ;
RECT 42600.0 480000.0 43800.0 481200.0 ;
RECT 37950.0 493800.0 36000.0 495000.0 ;
RECT 49800.0 493800.0 47850.0 495000.0 ;
RECT 48450.0 489000.0 50250.0 490200.0 ;
RECT 39150.0 489000.0 35550.0 490200.0 ;
RECT 48450.0 491700.0 39150.0 492600.0 ;
RECT 39150.0 489000.0 37950.0 490200.0 ;
RECT 39150.0 491400.0 37950.0 492600.0 ;
RECT 39150.0 491400.0 37950.0 492600.0 ;
RECT 39150.0 489000.0 37950.0 490200.0 ;
RECT 48450.0 489000.0 47250.0 490200.0 ;
RECT 48450.0 491400.0 47250.0 492600.0 ;
RECT 48450.0 491400.0 47250.0 492600.0 ;
RECT 48450.0 489000.0 47250.0 490200.0 ;
RECT 38550.0 493800.0 37350.0 495000.0 ;
RECT 48450.0 493800.0 47250.0 495000.0 ;
RECT 43800.0 489600.0 42600.0 490800.0 ;
RECT 43800.0 489600.0 42600.0 490800.0 ;
RECT 43650.0 492150.0 42750.0 493050.0 ;
RECT 36450.0 487200.0 35550.0 496800.0 ;
RECT 50250.0 487200.0 49350.0 496800.0 ;
RECT 42600.0 489600.0 43800.0 490800.0 ;
RECT 34050.0 480600.0 36000.0 479400.0 ;
RECT 22200.0 480600.0 24150.0 479400.0 ;
RECT 23550.0 485400.0 21750.0 484200.0 ;
RECT 32850.0 485400.0 36450.0 484200.0 ;
RECT 23550.0 482700.0 32850.0 481800.0 ;
RECT 32850.0 485400.0 34050.0 484200.0 ;
RECT 32850.0 483000.0 34050.0 481800.0 ;
RECT 32850.0 483000.0 34050.0 481800.0 ;
RECT 32850.0 485400.0 34050.0 484200.0 ;
RECT 23550.0 485400.0 24750.0 484200.0 ;
RECT 23550.0 483000.0 24750.0 481800.0 ;
RECT 23550.0 483000.0 24750.0 481800.0 ;
RECT 23550.0 485400.0 24750.0 484200.0 ;
RECT 33450.0 480600.0 34650.0 479400.0 ;
RECT 23550.0 480600.0 24750.0 479400.0 ;
RECT 28200.0 484800.0 29400.0 483600.0 ;
RECT 28200.0 484800.0 29400.0 483600.0 ;
RECT 28350.0 482250.0 29250.0 481350.0 ;
RECT 35550.0 487200.0 36450.0 477600.0 ;
RECT 21750.0 487200.0 22650.0 477600.0 ;
RECT 28200.0 483600.0 29400.0 484800.0 ;
RECT 34050.0 471000.0 36000.0 469800.0 ;
RECT 22200.0 471000.0 24150.0 469800.0 ;
RECT 23550.0 475800.0 21750.0 474600.0 ;
RECT 32850.0 475800.0 36450.0 474600.0 ;
RECT 23550.0 473100.0 32850.0 472200.0 ;
RECT 32850.0 475800.0 34050.0 474600.0 ;
RECT 32850.0 473400.0 34050.0 472200.0 ;
RECT 32850.0 473400.0 34050.0 472200.0 ;
RECT 32850.0 475800.0 34050.0 474600.0 ;
RECT 23550.0 475800.0 24750.0 474600.0 ;
RECT 23550.0 473400.0 24750.0 472200.0 ;
RECT 23550.0 473400.0 24750.0 472200.0 ;
RECT 23550.0 475800.0 24750.0 474600.0 ;
RECT 33450.0 471000.0 34650.0 469800.0 ;
RECT 23550.0 471000.0 24750.0 469800.0 ;
RECT 28200.0 475200.0 29400.0 474000.0 ;
RECT 28200.0 475200.0 29400.0 474000.0 ;
RECT 28350.0 472650.0 29250.0 471750.0 ;
RECT 35550.0 477600.0 36450.0 468000.0 ;
RECT 21750.0 477600.0 22650.0 468000.0 ;
RECT 28200.0 474000.0 29400.0 475200.0 ;
RECT 34050.0 461400.0 36000.0 460200.0 ; RECT 34050.0 461400.0 36000.0 460200.0 ;
RECT 22200.0 461400.0 24150.0 460200.0 ; RECT 22200.0 461400.0 24150.0 460200.0 ;
RECT 23550.0 466200.0 21750.0 465000.0 ; RECT 23550.0 466200.0 21750.0 465000.0 ;
@ -4512,22 +4431,29 @@ MACRO sram_2_16_1_scn3me_subm
RECT 21750.0 420000.0 22650.0 410400.0 ; RECT 21750.0 420000.0 22650.0 410400.0 ;
RECT 28200.0 416400.0 29400.0 417600.0 ; RECT 28200.0 416400.0 29400.0 417600.0 ;
RECT 42600.0 415200.0 43800.0 416400.0 ; RECT 42600.0 415200.0 43800.0 416400.0 ;
RECT 42600.0 453600.0 43800.0 454800.0 ; RECT 42600.0 444000.0 43800.0 445200.0 ;
RECT 42600.0 492000.0 43800.0 493200.0 ; RECT 42600.0 472800.0 43800.0 474000.0 ;
RECT 28200.0 452400.0 29400.0 453600.0 ; RECT 28200.0 442800.0 29400.0 444000.0 ;
RECT 42600.0 412800.0 43800.0 414000.0 ; RECT 42600.0 412800.0 43800.0 414000.0 ;
RECT 28350.0 410400.0 29250.0 414150.0 ; RECT 28350.0 410400.0 29250.0 414150.0 ;
RECT 35550.0 410400.0 36450.0 496800.0 ; RECT 35550.0 410400.0 36450.0 477600.0 ;
RECT 21750.0 410400.0 22650.0 496800.0 ; RECT 21750.0 410400.0 22650.0 477600.0 ;
RECT 49350.0 410400.0 50250.0 496800.0 ; RECT 49350.0 410400.0 50250.0 477600.0 ;
RECT 16800.0 395400.0 6600.0 381600.0 ; RECT 16800.0 395400.0 6600.0 381600.0 ;
RECT 16800.0 395400.0 6600.0 409200.0 ; RECT 16800.0 395400.0 6600.0 409200.0 ;
RECT 16800.0 423000.0 6600.0 409200.0 ; RECT 16800.0 423000.0 6600.0 409200.0 ;
RECT 16800.0 423000.0 6600.0 436800.0 ;
RECT 16800.0 450600.0 6600.0 436800.0 ;
RECT 17400.0 396900.0 6000.0 398100.0 ; RECT 17400.0 396900.0 6000.0 398100.0 ;
RECT 17400.0 420300.0 6000.0 421500.0 ; RECT 17400.0 420300.0 6000.0 421500.0 ;
RECT 17400.0 424500.0 6000.0 425700.0 ;
RECT 17400.0 447900.0 6000.0 449100.0 ;
RECT 17400.0 408600.0 6000.0 409500.0 ; RECT 17400.0 408600.0 6000.0 409500.0 ;
RECT 17400.0 436200.0 6000.0 437100.0 ;
RECT 22350.0 396900.0 21150.0 398100.0 ; RECT 22350.0 396900.0 21150.0 398100.0 ;
RECT 22350.0 420300.0 21150.0 421500.0 ; RECT 22350.0 420300.0 21150.0 421500.0 ;
RECT 22350.0 424500.0 21150.0 425700.0 ;
RECT 22350.0 447900.0 21150.0 449100.0 ;
RECT 22200.0 410400.0 21000.0 411600.0 ; RECT 22200.0 410400.0 21000.0 411600.0 ;
RECT 22800.0 370800.0 21600.0 372000.0 ; RECT 22800.0 370800.0 21600.0 372000.0 ;
RECT 16200.0 371400.0 17400.0 372600.0 ; RECT 16200.0 371400.0 17400.0 372600.0 ;
@ -4538,7 +4464,7 @@ MACRO sram_2_16_1_scn3me_subm
RECT 12600.0 375600.0 13800.0 376800.0 ; RECT 12600.0 375600.0 13800.0 376800.0 ;
RECT 43800.0 362400.0 42900.0 412800.0 ; RECT 43800.0 362400.0 42900.0 412800.0 ;
RECT 29250.0 362400.0 28350.0 375750.0 ; RECT 29250.0 362400.0 28350.0 375750.0 ;
RECT 4500.0 362400.0 3600.0 425250.0 ; RECT 4500.0 362400.0 3600.0 452850.0 ;
RECT 36450.0 362400.0 35550.0 410400.0 ; RECT 36450.0 362400.0 35550.0 410400.0 ;
RECT 22650.0 362400.0 21750.0 372000.0 ; RECT 22650.0 362400.0 21750.0 372000.0 ;
RECT 50250.0 362400.0 49350.0 410400.0 ; RECT 50250.0 362400.0 49350.0 410400.0 ;
@ -5348,29 +5274,25 @@ MACRO sram_2_16_1_scn3me_subm
RECT 10800.0 288450.0 9600.0 287250.0 ; RECT 10800.0 288450.0 9600.0 287250.0 ;
RECT 31200.0 263100.0 30000.0 261900.0 ; RECT 31200.0 263100.0 30000.0 261900.0 ;
RECT 31200.0 288450.0 30000.0 287250.0 ; RECT 31200.0 288450.0 30000.0 287250.0 ;
RECT 22650.0 372000.0 21750.0 430200.0 ; RECT 22650.0 372000.0 21750.0 457800.0 ;
RECT 17250.0 372000.0 16350.0 425400.0 ; RECT 17250.0 372000.0 16350.0 453000.0 ;
RECT 7050.0 372000.0 6150.0 425400.0 ; RECT 7050.0 372000.0 6150.0 453000.0 ;
RECT 20400.0 376200.0 19500.0 384300.0 ; RECT 20400.0 376200.0 19500.0 384300.0 ;
RECT 13650.0 376200.0 12750.0 381000.0 ; RECT 13650.0 376200.0 12750.0 381000.0 ;
RECT 42750.0 415800.0 43650.0 423000.0 ; RECT 42750.0 415800.0 43650.0 423000.0 ;
RECT 42750.0 423000.0 43650.0 432600.0 ; RECT 42750.0 423000.0 43650.0 432600.0 ;
RECT 42750.0 432600.0 43650.0 442200.0 ; RECT 42750.0 432600.0 43650.0 442200.0 ;
RECT 42750.0 442200.0 43650.0 451800.0 ; RECT 42750.0 444600.0 43650.0 451800.0 ;
RECT 42750.0 454200.0 43650.0 461400.0 ; RECT 42750.0 451800.0 43650.0 461400.0 ;
RECT 42750.0 461400.0 43650.0 471000.0 ; RECT 42750.0 461400.0 43650.0 471000.0 ;
RECT 42750.0 471000.0 43650.0 480600.0 ; RECT 35550.0 472950.0 36450.0 473850.0 ;
RECT 42750.0 480600.0 43650.0 490200.0 ; RECT 35550.0 464550.0 36450.0 465450.0 ;
RECT 35550.0 492150.0 36450.0 493050.0 ; RECT 36000.0 472950.0 43200.0 473850.0 ;
RECT 35550.0 483750.0 36450.0 484650.0 ; RECT 35550.0 465000.0 36450.0 473400.0 ;
RECT 36000.0 492150.0 43200.0 493050.0 ; RECT 28800.0 464550.0 36000.0 465450.0 ;
RECT 35550.0 484200.0 36450.0 492600.0 ;
RECT 28800.0 483750.0 36000.0 484650.0 ;
RECT 28350.0 474600.0 29250.0 484200.0 ;
RECT 28350.0 465000.0 29250.0 474600.0 ;
RECT 28350.0 455400.0 29250.0 465000.0 ; RECT 28350.0 455400.0 29250.0 465000.0 ;
RECT 28350.0 445800.0 29250.0 453000.0 ; RECT 28350.0 445800.0 29250.0 455400.0 ;
RECT 28350.0 436200.0 29250.0 445800.0 ; RECT 28350.0 436200.0 29250.0 443400.0 ;
RECT 28350.0 426600.0 29250.0 436200.0 ; RECT 28350.0 426600.0 29250.0 436200.0 ;
RECT 28350.0 417000.0 29250.0 426600.0 ; RECT 28350.0 417000.0 29250.0 426600.0 ;
RECT 42600.0 422400.0 43800.0 423600.0 ; RECT 42600.0 422400.0 43800.0 423600.0 ;
@ -5379,10 +5301,6 @@ MACRO sram_2_16_1_scn3me_subm
RECT 42600.0 451200.0 43800.0 452400.0 ; RECT 42600.0 451200.0 43800.0 452400.0 ;
RECT 42600.0 460800.0 43800.0 462000.0 ; RECT 42600.0 460800.0 43800.0 462000.0 ;
RECT 42600.0 470400.0 43800.0 471600.0 ; RECT 42600.0 470400.0 43800.0 471600.0 ;
RECT 42600.0 480000.0 43800.0 481200.0 ;
RECT 42600.0 489600.0 43800.0 490800.0 ;
RECT 28200.0 483600.0 29400.0 484800.0 ;
RECT 28200.0 474000.0 29400.0 475200.0 ;
RECT 28200.0 464400.0 29400.0 465600.0 ; RECT 28200.0 464400.0 29400.0 465600.0 ;
RECT 28200.0 454800.0 29400.0 456000.0 ; RECT 28200.0 454800.0 29400.0 456000.0 ;
RECT 28200.0 445200.0 29400.0 446400.0 ; RECT 28200.0 445200.0 29400.0 446400.0 ;
@ -5390,18 +5308,22 @@ MACRO sram_2_16_1_scn3me_subm
RECT 28200.0 426000.0 29400.0 427200.0 ; RECT 28200.0 426000.0 29400.0 427200.0 ;
RECT 28200.0 416400.0 29400.0 417600.0 ; RECT 28200.0 416400.0 29400.0 417600.0 ;
RECT 42600.0 415200.0 43800.0 416400.0 ; RECT 42600.0 415200.0 43800.0 416400.0 ;
RECT 42600.0 453600.0 43800.0 454800.0 ; RECT 42600.0 444000.0 43800.0 445200.0 ;
RECT 42600.0 492000.0 43800.0 493200.0 ; RECT 42600.0 472800.0 43800.0 474000.0 ;
RECT 28200.0 452400.0 29400.0 453600.0 ; RECT 28200.0 442800.0 29400.0 444000.0 ;
RECT 16800.0 395400.0 6600.0 381600.0 ; RECT 16800.0 395400.0 6600.0 381600.0 ;
RECT 16800.0 395400.0 6600.0 409200.0 ; RECT 16800.0 395400.0 6600.0 409200.0 ;
RECT 16800.0 423000.0 6600.0 409200.0 ; RECT 16800.0 423000.0 6600.0 409200.0 ;
RECT 13800.0 396000.0 12600.0 426600.0 ; RECT 16800.0 423000.0 6600.0 436800.0 ;
RECT 10800.0 394800.0 9600.0 425400.0 ; RECT 16800.0 450600.0 6600.0 436800.0 ;
RECT 17400.0 394800.0 16200.0 425400.0 ; RECT 13800.0 396000.0 12600.0 454200.0 ;
RECT 7200.0 394800.0 6000.0 425400.0 ; RECT 10800.0 394800.0 9600.0 453000.0 ;
RECT 17400.0 394800.0 16200.0 453000.0 ;
RECT 7200.0 394800.0 6000.0 453000.0 ;
RECT 22350.0 396900.0 21150.0 398100.0 ; RECT 22350.0 396900.0 21150.0 398100.0 ;
RECT 22350.0 420300.0 21150.0 421500.0 ; RECT 22350.0 420300.0 21150.0 421500.0 ;
RECT 22350.0 424500.0 21150.0 425700.0 ;
RECT 22350.0 447900.0 21150.0 449100.0 ;
RECT 22200.0 410400.0 21000.0 411600.0 ; RECT 22200.0 410400.0 21000.0 411600.0 ;
RECT 22800.0 370800.0 21600.0 372000.0 ; RECT 22800.0 370800.0 21600.0 372000.0 ;
RECT 16200.0 371400.0 17400.0 372600.0 ; RECT 16200.0 371400.0 17400.0 372600.0 ;

102
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C.lib → compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){ library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup"; delay_model : "table_lookup";
time_unit : "1ns" ; time_unit : "1ns" ;
voltage_unit : "1v" ; voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
capacitive_load_unit(1 ,fF) ; capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ; leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ; pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){ operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ; voltage : 5.0 ;
temperature : 25; temperature : 25;
} }
@ -21,6 +22,9 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ; slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ; slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ; default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ; default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ; default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
index_2("0.0125, 0.05, 0.4"); index_2("0.0125, 0.05, 0.4");
} }
default_operating_conditions : TT; default_operating_conditions : OC;
type (DATA){ type (DATA){
@ -74,12 +78,18 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 122426.46; area : 134589.78;
leakage_power () {
when : "CSb";
value : 0.0011563287;
}
cell_leakage_power : 0;
bus(DATA){ bus(DATA){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : inout;
max_capacitance : 78.5936; max_capacitance : 78.5936;
min_capacitance : 2.45605;
three_state : "!OEb & !clk"; three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_scn3me_subm){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("11.756062");
}
fall_power(scalar){
values("7.1840422");
}
}
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -126,38 +127,29 @@ cell (sram_2_16_1_scn3me_subm){
"-0.052, -0.059, -0.132"); "-0.052, -0.059, -0.132");
} }
} }
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("10.730552");
}
fall_power(scalar){
values("10.584523");
}
}
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
timing_type : falling_edge; timing_type : falling_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.458, 0.503, 0.87",\ values("0.473, 0.519, 0.888",\
"0.461, 0.505, 0.873",\ "0.476, 0.522, 0.891",\
"0.5, 0.544, 0.911"); "0.516, 0.56, 0.928");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.573, 0.649, 1.249",\ values("0.582, 0.655, 1.256",\
"0.576, 0.651, 1.252",\ "0.585, 0.658, 1.259",\
"0.616, 0.69, 1.289"); "0.625, 0.697, 1.295");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.153, 0.232, 1.084",\ values("0.154, 0.233, 1.086",\
"0.153, 0.233, 1.084",\ "0.155, 0.234, 1.086",\
"0.156, 0.236, 1.084"); "0.158, 0.237, 1.086");
} }
fall_transition(CELL_TABLE) { fall_transition(CELL_TABLE) {
values("0.277, 0.355, 1.499",\ values("0.278, 0.359, 1.499",\
"0.277, 0.357, 1.499",\ "0.278, 0.361, 1.499",\
"0.278, 0.362, 1.499"); "0.28, 0.367, 1.5");
} }
} }
} }
@ -168,7 +160,6 @@ cell (sram_2_16_1_scn3me_subm){
direction : input; direction : input;
capacitance : 9.8242; capacitance : 9.8242;
max_transition : 0.4; max_transition : 0.4;
fanout_load : 1.000000;
pin(ADDR[3:0]){ pin(ADDR[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
@ -304,24 +295,51 @@ cell (sram_2_16_1_scn3me_subm){
clock : true; clock : true;
direction : input; direction : input;
capacitance : 9.8242; capacitance : 9.8242;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("4.91866674167");
}
fall_power(scalar){
values("4.91866674167");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("5.72315586111");
}
fall_power(scalar){
values("5.72315586111");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){ timing(){
timing_type :"min_pulse_width"; timing_type :"min_pulse_width";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("2.344"); values("1.875");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("2.344"); values("1.875");
} }
} }
timing(){ timing(){
timing_type :"minimum_period"; timing_type :"minimum_period";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("4.688"); values("3.75");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("4.688"); values("3.75");
} }
} }
} }

70
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C_analytical.lib → compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){ library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup"; delay_model : "table_lookup";
time_unit : "1ns" ; time_unit : "1ns" ;
voltage_unit : "1v" ; voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
capacitive_load_unit(1 ,fF) ; capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ; leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ; pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){ operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ; voltage : 5.0 ;
temperature : 25; temperature : 25;
} }
@ -21,6 +22,9 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ; slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ; slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ; default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ; default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ; default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
index_2("0.0125, 0.05, 0.4"); index_2("0.0125, 0.05, 0.4");
} }
default_operating_conditions : TT; default_operating_conditions : OC;
type (DATA){ type (DATA){
@ -74,12 +78,18 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 122426.46; area : 134589.78;
leakage_power () {
when : "CSb";
value : 0;
}
cell_leakage_power : 0;
bus(DATA){ bus(DATA){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : inout;
max_capacitance : 78.5936; max_capacitance : 78.5936;
min_capacitance : 2.45605;
three_state : "!OEb & !clk"; three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_scn3me_subm){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_scn3me_subm){
"0.001, 0.001, 0.001"); "0.001, 0.001, 0.001");
} }
} }
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
@ -149,12 +141,12 @@ cell (sram_2_16_1_scn3me_subm){
"0.556, 0.603, 1.044",\ "0.556, 0.603, 1.044",\
"0.556, 0.603, 1.044"); "0.556, 0.603, 1.044");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.024, 0.081, 0.61",\ values("0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61",\ "0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61"); "0.024, 0.081, 0.61");
} }
fall_transition(CELL_TABLE) { fall_transition(CELL_TABLE) {
values("0.024, 0.081, 0.61",\ values("0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61",\ "0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61"); "0.024, 0.081, 0.61");
@ -168,7 +160,6 @@ cell (sram_2_16_1_scn3me_subm){
direction : input; direction : input;
capacitance : 9.8242; capacitance : 9.8242;
max_transition : 0.4; max_transition : 0.4;
fanout_load : 1.000000;
pin(ADDR[3:0]){ pin(ADDR[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
@ -304,6 +295,33 @@ cell (sram_2_16_1_scn3me_subm){
clock : true; clock : true;
direction : input; direction : input;
capacitance : 9.8242; capacitance : 9.8242;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){ timing(){
timing_type :"min_pulse_width"; timing_type :"min_pulse_width";
related_pin : clk; related_pin : clk;

90
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C_pruned.lib → compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){ library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup"; delay_model : "table_lookup";
time_unit : "1ns" ; time_unit : "1ns" ;
voltage_unit : "1v" ; voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
capacitive_load_unit(1 ,fF) ; capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ; leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ; pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){ operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ; voltage : 5.0 ;
temperature : 25; temperature : 25;
} }
@ -21,6 +22,9 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ; slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ; slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ; default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ; default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ; default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
index_2("0.0125, 0.05, 0.4"); index_2("0.0125, 0.05, 0.4");
} }
default_operating_conditions : TT; default_operating_conditions : OC;
type (DATA){ type (DATA){
@ -74,12 +78,18 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 122426.46; area : 134589.78;
leakage_power () {
when : "CSb";
value : 0.0011563287;
}
cell_leakage_power : 0;
bus(DATA){ bus(DATA){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : inout;
max_capacitance : 78.5936; max_capacitance : 78.5936;
min_capacitance : 2.45605;
three_state : "!OEb & !clk"; three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_scn3me_subm){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("11.756062");
}
fall_power(scalar){
values("7.1840422");
}
}
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_scn3me_subm){
"-0.052, -0.059, -0.132"); "-0.052, -0.059, -0.132");
} }
} }
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("10.730552");
}
fall_power(scalar){
values("10.584523");
}
}
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
@ -145,19 +137,19 @@ cell (sram_2_16_1_scn3me_subm){
"0.5, 0.544, 0.911"); "0.5, 0.544, 0.911");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.573, 0.649, 1.249",\ values("0.573, 0.645, 1.246",\
"0.576, 0.651, 1.252",\ "0.576, 0.648, 1.249",\
"0.616, 0.69, 1.289"); "0.616, 0.687, 1.286");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.153, 0.232, 1.084",\ values("0.153, 0.232, 1.084",\
"0.153, 0.233, 1.084",\ "0.153, 0.233, 1.084",\
"0.156, 0.236, 1.084"); "0.156, 0.236, 1.084");
} }
fall_transition(CELL_TABLE) { fall_transition(CELL_TABLE) {
values("0.277, 0.355, 1.499",\ values("0.277, 0.36, 1.499",\
"0.277, 0.357, 1.499",\ "0.277, 0.362, 1.499",\
"0.278, 0.362, 1.499"); "0.278, 0.37, 1.5");
} }
} }
} }
@ -168,7 +160,6 @@ cell (sram_2_16_1_scn3me_subm){
direction : input; direction : input;
capacitance : 9.8242; capacitance : 9.8242;
max_transition : 0.4; max_transition : 0.4;
fanout_load : 1.000000;
pin(ADDR[3:0]){ pin(ADDR[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
@ -304,24 +295,51 @@ cell (sram_2_16_1_scn3me_subm){
clock : true; clock : true;
direction : input; direction : input;
capacitance : 9.8242; capacitance : 9.8242;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("4.39065104738");
}
fall_power(scalar){
values("4.39065104738");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("5.00353945572");
}
fall_power(scalar){
values("5.00353945572");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){ timing(){
timing_type :"min_pulse_width"; timing_type :"min_pulse_width";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("2.344"); values("1.875");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("2.344"); values("1.875");
} }
} }
timing(){ timing(){
timing_type :"minimum_period"; timing_type :"minimum_period";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("4.688"); values("3.75");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("4.688"); values("3.75");
} }
} }
} }

4
compiler/verify/calibre.py
View File

@ -103,7 +103,7 @@ def run_drc(cell_name, gds_name):
OPTS.openram_temp, OPTS.openram_temp,
errfile, errfile,
outfile) outfile)
debug.info(1, cmd) debug.info(2, cmd)
os.system(cmd) os.system(cmd)
os.chdir(cwd) os.chdir(cwd)
@ -191,7 +191,7 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
OPTS.openram_temp, OPTS.openram_temp,
errfile, errfile,
outfile) outfile)
debug.info(1, cmd) debug.info(2, cmd)
os.system(cmd) os.system(cmd)
os.chdir(cwd) os.chdir(cwd)

4
compiler/verify/magic.py
View File

@ -152,7 +152,7 @@ def run_drc(cell_name, gds_name, extract=False):
cmd = "{0}run_drc.sh 2> {1} 1> {2}".format(OPTS.openram_temp, cmd = "{0}run_drc.sh 2> {1} 1> {2}".format(OPTS.openram_temp,
errfile, errfile,
outfile) outfile)
debug.info(1, cmd) debug.info(2, cmd)
os.system(cmd) os.system(cmd)
os.chdir(cwd) os.chdir(cwd)
@ -204,7 +204,7 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
cmd = "{0}run_lvs.sh lvs 2> {1} 1> {2}".format(OPTS.openram_temp, cmd = "{0}run_lvs.sh lvs 2> {1} 1> {2}".format(OPTS.openram_temp,
errfile, errfile,
outfile) outfile)
debug.info(1, cmd) debug.info(2, cmd)
os.system(cmd) os.system(cmd)
os.chdir(cwd) os.chdir(cwd)

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2
lib/Makefile
View File

@ -4,7 +4,7 @@ SUBDIRSCLEAN=$(addsuffix clean,$(SUBDIRS))
all: $(SUBDIRS) all: $(SUBDIRS)
$(SUBDIRS): $(SUBDIRS):
$(MAKE) -C $@ $(MAKE) -k -C $@
clean: clean:
for dir in $(SUBDIRS); do \ for dir in $(SUBDIRS); do \

5
lib/README.md Normal file
View File

@ -0,0 +1,5 @@
This directory contains a set of common sizes based on
discussions with users. All of the files are pre-computed
to that common-case users don't need to setup/use OpenRAM.
The results will be updated automatically as improvements
are made to OpenRAM.

6
lib/freepdk45/Makefile
View File

@ -1,7 +1,7 @@
CUR_DIR = $(shell pwd) CUR_DIR = $(shell pwd)
TEST_DIR = ${CUR_DIR}/tests TEST_DIR = ${CUR_DIR}/tests
MAKEFLAGS += -j 2 #MAKEFLAGS += -j 2
CONFIG_DIR = configs CONFIG_DIR = configs
OUT_DIRS = sp lib lef gds verilog OUT_DIRS = sp lib lef gds verilog
@ -14,7 +14,9 @@ all : $(SPICES)
# Characterize and perform DRC/LVS # Characterize and perform DRC/LVS
OPTS = -c OPTS = -c
# Do not characterize or perform DRC/LVS # Do not characterize or perform DRC/LVS
#OPTS = -n #OPTS += -n
# Verbosity
OPTS += -v
%.sp : %.py %.sp : %.py
$(eval bname=$(basename $(notdir $<))) $(eval bname=$(basename $(notdir $<)))
openram.py $(OPTS) $< 2>&1 > $(bname).log openram.py $(OPTS) $< 2>&1 > $(bname).log

3
lib/freepdk45/configs/sram_1rw_128b_1024w_1bank_freepdk45.py
View File

@ -3,3 +3,6 @@ num_words = 1024
num_banks = 1 num_banks = 1
tech_name = "freepdk45" tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

8
lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py Normal file
View File

@ -0,0 +1,8 @@
word_size = 128
num_words = 1024
num_banks = 2
tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

8
lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py Normal file
View File

@ -0,0 +1,8 @@
word_size = 128
num_words = 1024
num_banks = 4
tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

3
lib/freepdk45/configs/sram_1rw_32b_1024w_1bank_freepdk45.py
View File

@ -3,3 +3,6 @@ num_words = 1024
num_banks = 1 num_banks = 1
tech_name = "freepdk45" tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

3
lib/freepdk45/configs/sram_1rw_32b_2048w_1bank_freepdk45.py
View File

@ -3,3 +3,6 @@ num_words = 2048
num_banks = 1 num_banks = 1
tech_name = "freepdk45" tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

8
lib/freepdk45/configs/sram_1rw_32b_256w_1bank_freepdk45.py Normal file
View File

@ -0,0 +1,8 @@
word_size = 32
num_words = 256
num_banks = 1
tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

8
lib/freepdk45/configs/sram_1rw_32b_512w_1bank_freepdk45.py Normal file
View File

@ -0,0 +1,8 @@
word_size = 32
num_words = 512
num_banks = 1
tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

8
lib/freepdk45/configs/sram_1rw_64b_1024w_1bank_freepdk45.py Normal file
View File

@ -0,0 +1,8 @@
word_size = 64
num_words = 1024
num_banks = 1
tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

8
lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py Normal file
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@ -0,0 +1,8 @@
word_size = 64
num_words = 1024
num_banks = 2
tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

3
lib/freepdk45/configs/sram_1rw_8b_1024w_4bank_freepdk45.py → lib/freepdk45/configs/sram_1rw_8b_1024w_1bank_freepdk45.py
View File

@ -3,3 +3,6 @@ num_words = 1024
num_banks = 4 num_banks = 4
tech_name = "freepdk45" tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

3
lib/freepdk45/configs/sram_1rw_8b_256w_1bank_freepdk45.py
View File

@ -3,3 +3,6 @@ num_words = 256
num_banks = 1 num_banks = 1
tech_name = "freepdk45" tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

3
lib/freepdk45/configs/sram_1rw_8b_512w_4bank_freepdk45.py → lib/freepdk45/configs/sram_1rw_8b_512w_1bank_freepdk45.py
View File

@ -3,3 +3,6 @@ num_words = 512
num_banks = 4 num_banks = 4
tech_name = "freepdk45" tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]

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lib/freepdk45/lib/sram_1rw_128b_1024w_1bank_freepdk45_TT_1p0V_25C.lib Normal file
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@ -0,0 +1,347 @@
library (sram_1rw_128b_1024w_1bank_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.00125, 0.005, 0.04");
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 128;
bit_from : 0;
bit_to : 127;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 10;
bit_from : 0;
bit_to : 9;
}
cell (sram_1rw_128b_1024w_1bank_freepdk45){
memory(){
type : ram;
address_width : 10;
word_width : 128;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 146602.501987;
leakage_power () {
when : "CSb";
value : 0.56084648;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
memory_read(){
address : ADDR;
}
pin(DATA[127:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("3.107, 3.109, 3.117",\
"3.109, 3.11, 3.118",\
"3.114, 3.115, 3.123");
}
cell_fall(CELL_TABLE) {
values("0.27, 0.274, 0.297",\
"0.271, 0.274, 0.298",\
"0.277, 0.28, 0.303");
}
rise_transition(CELL_TABLE) {
values("0.023, 0.024, 0.034",\
"0.023, 0.024, 0.034",\
"0.023, 0.024, 0.034");
}
fall_transition(CELL_TABLE) {
values("0.055, 0.057, 0.077",\
"0.055, 0.057, 0.077",\
"0.055, 0.058, 0.077");
}
}
}
}
bus(ADDR){
bus_type : ADDR;
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR[9:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
}
pin(CSb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.359934198778");
}
fall_power(scalar){
values("0.359934198778");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.377816169333");
}
fall_power(scalar){
values("0.377816169333");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("2.969");
}
fall_constraint(scalar) {
values("2.969");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("5.938");
}
fall_constraint(scalar) {
values("5.938");
}
}
}
}
}

347
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library (sram_1rw_128b_1024w_4bank_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.00125, 0.005, 0.04");
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 128;
bit_from : 0;
bit_to : 127;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 10;
bit_from : 0;
bit_to : 9;
}
cell (sram_1rw_128b_1024w_4bank_freepdk45){
memory(){
type : ram;
address_width : 10;
word_width : 128;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 178744.321438;
leakage_power () {
when : "CSb";
value : 1.2037325;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
memory_read(){
address : ADDR;
}
pin(DATA[127:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.177, 0.178, 0.186",\
"0.177, 0.178, 0.186",\
"0.183, 0.184, 0.192");
}
cell_fall(CELL_TABLE) {
values("0.158, 0.159, 0.168",\
"0.159, 0.16, 0.168",\
"0.164, 0.165, 0.174");
}
rise_transition(CELL_TABLE) {
values("0.08, 0.081, 0.091",\
"0.08, 0.081, 0.091",\
"0.081, 0.082, 0.091");
}
fall_transition(CELL_TABLE) {
values("0.077, 0.079, 0.093",\
"0.077, 0.079, 0.093",\
"0.078, 0.079, 0.093");
}
}
}
}
bus(ADDR){
bus_type : ADDR;
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR[9:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
}
pin(CSb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.719680893333");
}
fall_power(scalar){
values("0.719680893333");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.767111023611");
}
fall_power(scalar){
values("0.767111023611");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("1.0155");
}
fall_constraint(scalar) {
values("1.0155");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("2.031");
}
fall_constraint(scalar) {
values("2.031");
}
}
}
}
}

347
lib/freepdk45/lib/sram_1rw_32b_1024w_1bank_freepdk45_TT_1p0V_25C.lib Normal file
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library (sram_1rw_32b_1024w_1bank_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.00125, 0.005, 0.04");
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 32;
bit_from : 0;
bit_to : 31;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 10;
bit_from : 0;
bit_to : 9;
}
cell (sram_1rw_32b_1024w_1bank_freepdk45){
memory(){
type : ram;
address_width : 10;
word_width : 32;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 42051.1147875;
leakage_power () {
when : "CSb";
value : 0.15279765;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
memory_read(){
address : ADDR;
}
pin(DATA[31:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("1.158, 1.159, 1.167",\
"1.158, 1.161, 1.167",\
"1.164, 1.165, 1.171");
}
cell_fall(CELL_TABLE) {
values("0.171, 0.173, 0.186",\
"0.172, 0.173, 0.186",\
"0.177, 0.179, 0.192");
}
rise_transition(CELL_TABLE) {
values("0.02, 0.021, 0.032",\
"0.02, 0.021, 0.032",\
"0.02, 0.021, 0.031");
}
fall_transition(CELL_TABLE) {
values("0.065, 0.063, 0.058",\
"0.065, 0.063, 0.058",\
"0.066, 0.064, 0.058");
}
}
}
}
bus(ADDR){
bus_type : ADDR;
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR[9:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
}
pin(CSb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.177355641117");
}
fall_power(scalar){
values("0.177355641117");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.193822578894");
}
fall_power(scalar){
values("0.193822578894");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("1.094");
}
fall_constraint(scalar) {
values("1.094");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("2.188");
}
fall_constraint(scalar) {
values("2.188");
}
}
}
}
}

347
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library (sram_1rw_32b_2048w_1bank_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.00125, 0.005, 0.04");
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 32;
bit_from : 0;
bit_to : 31;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 11;
bit_from : 0;
bit_to : 10;
}
cell (sram_1rw_32b_2048w_1bank_freepdk45){
memory(){
type : ram;
address_width : 11;
word_width : 32;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 116044.35785;
leakage_power () {
when : "CSb";
value : 0.306155;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
memory_read(){
address : ADDR;
}
pin(DATA[31:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("1.22, 1.223, 1.23",\
"1.222, 1.221, 1.238",\
"1.232, 1.234, 1.237");
}
cell_fall(CELL_TABLE) {
values("0.235, 0.237, 0.251",\
"0.235, 0.237, 0.252",\
"0.241, 0.243, 0.257");
}
rise_transition(CELL_TABLE) {
values("0.02, 0.021, 0.032",\
"0.02, 0.022, 0.032",\
"0.02, 0.022, 0.032");
}
fall_transition(CELL_TABLE) {
values("0.131, 0.13, 0.072",\
"0.132, 0.13, 0.072",\
"0.132, 0.131, 0.074");
}
}
}
}
bus(ADDR){
bus_type : ADDR;
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR[10:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
}
pin(CSb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.37352892");
}
fall_power(scalar){
values("0.37352892");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.392384140556");
}
fall_power(scalar){
values("0.392384140556");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("1.172");
}
fall_constraint(scalar) {
values("1.172");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("2.344");
}
fall_constraint(scalar) {
values("2.344");
}
}
}
}
}

347
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library (sram_1rw_32b_256w_1bank_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.00125, 0.005, 0.04");
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 32;
bit_from : 0;
bit_to : 31;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 8;
bit_from : 0;
bit_to : 7;
}
cell (sram_1rw_32b_256w_1bank_freepdk45){
memory(){
type : ram;
address_width : 8;
word_width : 32;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 12335.4213125;
leakage_power () {
when : "CSb";
value : 0.040298101;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
memory_read(){
address : ADDR;
}
pin(DATA[31:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("1.116, 1.117, 1.124",\
"1.116, 1.117, 1.124",\
"1.122, 1.123, 1.13");
}
cell_fall(CELL_TABLE) {
values("0.118, 0.119, 0.132",\
"0.118, 0.12, 0.133",\
"0.124, 0.125, 0.138");
}
rise_transition(CELL_TABLE) {
values("0.02, 0.021, 0.031",\
"0.02, 0.021, 0.031",\
"0.02, 0.021, 0.031");
}
fall_transition(CELL_TABLE) {
values("0.028, 0.03, 0.046",\
"0.028, 0.03, 0.046",\
"0.029, 0.03, 0.046");
}
}
}
}
bus(ADDR){
bus_type : ADDR;
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR[7:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
}
pin(CSb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0644972321667");
}
fall_power(scalar){
values("0.0644972321667");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0770882050833");
}
fall_power(scalar){
values("0.0770882050833");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("1.0545");
}
fall_constraint(scalar) {
values("1.0545");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("2.109");
}
fall_constraint(scalar) {
values("2.109");
}
}
}
}
}

347
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library (sram_1rw_32b_512w_1bank_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.00125, 0.005, 0.04");
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 32;
bit_from : 0;
bit_to : 31;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 9;
bit_from : 0;
bit_to : 8;
}
cell (sram_1rw_32b_512w_1bank_freepdk45){
memory(){
type : ram;
address_width : 9;
word_width : 32;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 22454.71095;
leakage_power () {
when : "CSb";
value : 0.077704284;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
memory_read(){
address : ADDR;
}
pin(DATA[31:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("1.128, 1.129, 1.136",\
"1.128, 1.129, 1.136",\
"1.134, 1.135, 1.142");
}
cell_fall(CELL_TABLE) {
values("0.136, 0.138, 0.15",\
"0.137, 0.139, 0.151",\
"0.142, 0.144, 0.157");
}
rise_transition(CELL_TABLE) {
values("0.02, 0.021, 0.031",\
"0.02, 0.021, 0.031",\
"0.02, 0.021, 0.031");
}
fall_transition(CELL_TABLE) {
values("0.034, 0.036, 0.05",\
"0.035, 0.036, 0.05",\
"0.035, 0.036, 0.05");
}
}
}
}
bus(ADDR){
bus_type : ADDR;
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR[8:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
}
pin(CSb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0998806242278");
}
fall_power(scalar){
values("0.0998806242278");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.114319477006");
}
fall_power(scalar){
values("0.114319477006");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("1.094");
}
fall_constraint(scalar) {
values("1.094");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("2.188");
}
fall_constraint(scalar) {
values("2.188");
}
}
}
}
}

347
lib/freepdk45/lib/sram_1rw_64b_1024w_1bank_freepdk45_TT_1p0V_25C.lib Normal file
View File

@ -0,0 +1,347 @@
library (sram_1rw_64b_1024w_1bank_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.00125, 0.005, 0.04");
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 64;
bit_from : 0;
bit_to : 63;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 10;
bit_from : 0;
bit_to : 9;
}
cell (sram_1rw_64b_1024w_1bank_freepdk45){
memory(){
type : ram;
address_width : 10;
word_width : 64;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 76901.5771875;
leakage_power () {
when : "CSb";
value : 0.30184115;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
memory_read(){
address : ADDR;
}
pin(DATA[63:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("1.836, 1.837, 1.844",\
"1.837, 1.838, 1.846",\
"1.843, 1.843, 1.851");
}
cell_fall(CELL_TABLE) {
values("0.208, 0.211, 0.227",\
"0.209, 0.211, 0.228",\
"0.214, 0.217, 0.233");
}
rise_transition(CELL_TABLE) {
values("0.021, 0.022, 0.032",\
"0.021, 0.022, 0.032",\
"0.021, 0.022, 0.032");
}
fall_transition(CELL_TABLE) {
values("0.049, 0.05, 0.063",\
"0.049, 0.05, 0.063",\
"0.049, 0.05, 0.064");
}
}
}
}
bus(ADDR){
bus_type : ADDR;
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR[9:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
}
pin(CSb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.269265398756");
}
fall_power(scalar){
values("0.269265398756");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.293634058756");
}
fall_power(scalar){
values("0.293634058756");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("1.797");
}
fall_constraint(scalar) {
values("1.797");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("3.594");
}
fall_constraint(scalar) {
values("3.594");
}
}
}
}
}

112
compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_pruned.lib → lib/freepdk45/lib/sram_1rw_8b_256w_1bank_freepdk45_TT_1p0V_25C.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_freepdk45_TT_10V_25C_lib){ library (sram_1rw_8b_256w_1bank_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup"; delay_model : "table_lookup";
time_unit : "1ns" ; time_unit : "1ns" ;
voltage_unit : "1v" ; voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
capacitive_load_unit(1 ,fF) ; capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ; leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ; pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){ operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ; voltage : 1.0 ;
temperature : 25; temperature : 25;
} }
@ -21,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ; slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ; slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ; default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ; default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ; default_input_pin_cap : 1.0 ;
@ -45,41 +49,47 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
index_2("0.00125, 0.005, 0.04"); index_2("0.00125, 0.005, 0.04");
} }
default_operating_conditions : TT; default_operating_conditions : OC;
type (DATA){ type (DATA){
base_type : array; base_type : array;
data_type : bit; data_type : bit;
bit_width : 2; bit_width : 8;
bit_from : 0; bit_from : 0;
bit_to : 1; bit_to : 7;
} }
type (ADDR){ type (ADDR){
base_type : array; base_type : array;
data_type : bit; data_type : bit;
bit_width : 4; bit_width : 8;
bit_from : 0; bit_from : 0;
bit_to : 3; bit_to : 7;
} }
cell (sram_2_16_1_freepdk45){ cell (sram_1rw_8b_256w_1bank_freepdk45){
memory(){ memory(){
type : ram; type : ram;
address_width : 4; address_width : 8;
word_width : 2; word_width : 8;
} }
interface_timing : true; interface_timing : true;
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 918.5120625; area : 4498.9233125;
leakage_power () {
when : "CSb";
value : 0.011168618;
}
cell_leakage_power : 0;
bus(DATA){ bus(DATA){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : inout;
max_capacitance : 1.6728; max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk"; three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
@ -88,16 +98,7 @@ cell (sram_2_16_1_freepdk45){
memory_read(){ memory_read(){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DATA[7:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0.039115101");
}
fall_power(scalar){
values("0.026662611");
}
}
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -126,38 +127,29 @@ cell (sram_2_16_1_freepdk45){
"-0.004, -0.004, -0.016"); "-0.004, -0.004, -0.016");
} }
} }
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0.036300681");
}
fall_power(scalar){
values("0.041472985");
}
}
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
timing_type : falling_edge; timing_type : falling_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.054, 0.055, 0.061",\ values("0.556, 0.557, 0.564",\
"0.055, 0.055, 0.062",\ "0.556, 0.557, 0.564",\
"0.06, 0.061, 0.067"); "0.562, 0.563, 0.57");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.519, 0.52, 0.529",\ values("0.088, 0.089, 0.098",\
"0.519, 0.52, 0.53",\ "0.088, 0.09, 0.099",\
"0.525, 0.526, 0.535"); "0.094, 0.095, 0.104");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.013, 0.014, 0.026",\ values("0.02, 0.021, 0.031",\
"0.013, 0.014, 0.026",\ "0.02, 0.021, 0.031",\
"0.013, 0.015, 0.026"); "0.02, 0.021, 0.031");
} }
fall_transition(CELL_TABLE) { fall_transition(CELL_TABLE) {
values("0.027, 0.029, 0.043",\ values("0.03, 0.03, 0.041",\
"0.027, 0.029, 0.043",\ "0.031, 0.03, 0.041",\
"0.027, 0.029, 0.043"); "0.031, 0.031, 0.041");
} }
} }
} }
@ -168,8 +160,7 @@ cell (sram_2_16_1_freepdk45){
direction : input; direction : input;
capacitance : 0.2091; capacitance : 0.2091;
max_transition : 0.04; max_transition : 0.04;
fanout_load : 1.000000; pin(ADDR[7:0]){
pin(ADDR[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -304,6 +295,33 @@ cell (sram_2_16_1_freepdk45){
clock : true; clock : true;
direction : input; direction : input;
capacitance : 0.2091; capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0382237081278");
}
fall_power(scalar){
values("0.0382237081278");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0443502652111");
}
fall_power(scalar){
values("0.0443502652111");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){ timing(){
timing_type :"min_pulse_width"; timing_type :"min_pulse_width";
related_pin : clk; related_pin : clk;

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_12899_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_128b_1024w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_12899_temp/ =========|
|==============================================================================|
Output files are sram_1rw_128b_1024w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 128
Words: 1024
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 16:26:13.838687 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 15917 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 17508 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 21120 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 512
[verify.calibre/run_drc]: bitcell_array Geometries: 39847938 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 89090 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 48389 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 31747 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 41475 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 70385 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5877 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 75270 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 22788 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 70146 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 40382617 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_128b_1024w_1bank_freepdk45 Geometries: 40410068 Checks: 167 Errors: 0
** SRAM creation: 3506.7 seconds
SP: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.sp
** Spice writing: 0.6 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_12899_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 127 data bit
[characterizer.trim_spice/trim]: Keeping bl[511] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 10.0ns feasible_delay 3.1226964ns/0.30308602ns slew 0.034041887ns/0.077321978ns
[characterizer.delay/find_min_period]: MinPeriod Search: 5.0ns (ub: 10.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 7.5ns (ub: 10.0 lb: 5.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 6.25ns (ub: 7.5 lb: 5.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 5.625ns (ub: 6.25 lb: 5.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 5.9375ns (ub: 6.25 lb: 5.625)
[characterizer.delay/find_min_period]: MinPeriod Search: 5.78125ns (ub: 5.9375 lb: 5.625)
[characterizer.delay/analyze]: Min Period: 5.9375n with a delay of 3.1226964 / 0.30308602
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 16788.8 seconds
GDS: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.gds
** GDS: 9.0 seconds
LEF: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.lef
** LEF: 24.4 seconds
Verilog: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 20330.3 seconds

62
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@ -0,0 +1,62 @@
[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_18643_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_18643_temp/ =========|
|==============================================================================|
Output files are sram_1rw_128b_1024w_2bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 128
Words: 1024
Banks: 2
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 19:17:15.047539 seconds
[sram/compute_sizes]: Words per row: 2
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 15917 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 17508 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 21120 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 19924226 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 44546 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 24323 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 31747 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 41475 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 70385 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5290 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 75270 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 22788 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 70146 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 20381520 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 594 Checks: 167 Errors: 0
ERROR: file calibre.py: line 131: sram_1rw_128b_1024w_2bank_freepdk45 Geometries: 40824902 Checks: 167 Errors: 1
ERROR: file design.py: line 87: DRC failed for sram_1rw_128b_1024w_2bank_freepdk45

139
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@ -0,0 +1,139 @@
[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_5959_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_5959_temp/ =========|
|==============================================================================|
Output files are sram_1rw_128b_1024w_4bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 128
Words: 1024
Banks: 4
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 19:35:43.956230 seconds
[sram/compute_sizes]: Words per row: 2
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 26 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 7961 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 9383 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 12956 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 128 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 9962498 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 44546 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 24323 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 31747 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 41475 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 65237 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4703 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 75270 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 22788 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 35074 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 10340523 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 1181 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_128b_1024w_4bank_freepdk45 Geometries: 42826713 Checks: 167 Errors: 0
** SRAM creation: 439.1 seconds
SP: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.sp
** Spice writing: 0.2 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_5959_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 127 data bit
[characterizer.trim_spice/trim]: Keeping bl[254] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[511] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 0.19175762ns/0.17403244ns slew 0.091382364ns/0.093018754ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.953125ns (ub: 2.03125 lb: 1.875)
[characterizer.delay/analyze]: Min Period: 2.03125n with a delay of 0.19175762 / 0.17403244
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 35039.9 seconds
GDS: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.gds
** GDS: 5.3 seconds
LEF: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.lef
** LEF: 36.1 seconds
Verilog: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 35521.6 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_25677_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_1024w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_25677_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_1024w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 32
Words: 1024
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 07:05:54.597754 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 15917 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 17508 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 21120 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 9962370 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 22274 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 12101 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 7939 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 10371 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 70385 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5877 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 18822 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 5700 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 70146 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 10249561 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_1024w_1bank_freepdk45 Geometries: 10275380 Checks: 167 Errors: 0
** SRAM creation: 428.3 seconds
SP: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.sp
** Spice writing: 0.2 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_25677_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.1713644ns/0.19182711ns slew 0.03149035ns/0.058154194ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
[characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1713644 / 0.19182711
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 8034.5 seconds
GDS: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.gds
** GDS: 3.3 seconds
LEF: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.lef
** LEF: 10.1 seconds
Verilog: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 8477.4 seconds

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_17202_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_2048w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_17202_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_2048w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 32
Words: 2048
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 12:31:22.490074 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 103 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 31523 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 33446 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 37135 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 512 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 19924354 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 22274 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 12101 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 7939 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 10371 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_512rows Geometries: 242084 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 6464 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 18822 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 5700 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 140290 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 20402203 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_2048w_1bank_freepdk45 Geometries: 20447018 Checks: 167 Errors: 0
** SRAM creation: 1092.7 seconds
SP: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.sp
** Spice writing: 0.4 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_17202_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 11111111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[511] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.2374402ns/0.25744693ns slew 0.031680287ns/0.073574058ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.34375ns (ub: 2.5 lb: 2.1875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.265625ns (ub: 2.34375 lb: 2.1875)
[characterizer.delay/analyze]: Min Period: 2.34375n with a delay of 1.2374402 / 0.25744693
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 12972.2 seconds
GDS: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.gds
** GDS: 5.6 seconds
LEF: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.lef
** LEF: 17.3 seconds
Verilog: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 14089.0 seconds

137
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_18997_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_256w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_18997_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_256w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 32
Words: 256
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 17:53:13.665862 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 13 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3983 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 5321 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 8875 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 64 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 2490882 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 22274 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 12101 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 7939 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 10371 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 34473 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4703 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 18822 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 5700 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 17538 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 2641339 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_256w_1bank_freepdk45 Geometries: 2653124 Checks: 167 Errors: 0
** SRAM creation: 160.0 seconds
SP: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.sp
** Spice writing: 0.1 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_256w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_18997_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 11111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[63] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.1300259ns/0.13801474ns slew 0.031264005ns/0.046135884ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
[characterizer.delay/analyze]: Min Period: 2.109375n with a delay of 1.1300259 / 0.13801474
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 4457.6 seconds
GDS: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.gds
** GDS: 1.4 seconds
LEF: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.lef
** LEF: 3.6 seconds
Verilog: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 4623.9 seconds

137
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_3435_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_512w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_3435_temp/ =========|
|==============================================================================|
Output files are sram_1rw_32b_512w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 32
Words: 512
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 23:05:39.265001 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 26 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 7961 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 9383 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 12956 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 128 x 128
[verify.calibre/run_drc]: bitcell_array Geometries: 4981378 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 22274 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 12101 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 7939 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 10371 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 65237 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5290 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 18822 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 5700 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 35074 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 5189587 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_32b_512w_1bank_freepdk45 Geometries: 5206208 Checks: 167 Errors: 0
** SRAM creation: 219.2 seconds
SP: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.sp
** Spice writing: 0.1 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_512w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_3435_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 111111111 address
[characterizer.trim_spice/trim]: Keeping 31 data bit
[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[127] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.1419594ns/0.15656674ns slew 0.031336377ns/0.049918723ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
[characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
[characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1419594 / 0.15656674
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 5101.6 seconds
GDS: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.gds
** GDS: 1.8 seconds
LEF: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.lef
** LEF: 5.1 seconds
Verilog: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 5328.7 seconds

136
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_31317_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_64b_1024w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_31317_temp/ =========|
|==============================================================================|
Output files are sram_1rw_64b_1024w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 64
Words: 1024
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 09:27:13.909126 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 52 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 15917 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 17508 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 21120 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 256 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 19924226 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 44546 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 24197 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 15875 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 20739 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_256rows Geometries: 70385 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5877 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 37638 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 11396 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 70146 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 20293913 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_64b_1024w_1bank_freepdk45 Geometries: 20320276 Checks: 167 Errors: 0
** SRAM creation: 1075.6 seconds
SP: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.sp
** Spice writing: 0.3 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_31317_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 63 data bit
[characterizer.trim_spice/trim]: Keeping bl[255] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.850756ns/0.23319319ns slew 0.032157888ns/0.063655528ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 3.75ns (ub: 5.0 lb: 2.5)
[characterizer.delay/find_min_period]: MinPeriod Search: 3.125ns (ub: 3.75 lb: 2.5)
[characterizer.delay/find_min_period]: MinPeriod Search: 3.4375ns (ub: 3.75 lb: 3.125)
[characterizer.delay/find_min_period]: MinPeriod Search: 3.59375ns (ub: 3.75 lb: 3.4375)
[characterizer.delay/analyze]: Min Period: 3.59375n with a delay of 1.850756 / 0.23319319
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 9948.6 seconds
GDS: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.gds
** GDS: 5.9 seconds
LEF: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.lef
** LEF: 15.0 seconds
Verilog: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 11046.3 seconds

62
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_3114_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_3114_temp/ =========|
|==============================================================================|
Output files are sram_1rw_64b_1024w_2bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 64
Words: 1024
Banks: 2
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-23 19:10:19.014431 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 26 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 7961 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 9383 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 12956 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 128 x 256
[verify.calibre/run_drc]: bitcell_array Geometries: 9962498 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 44546 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 24197 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 15875 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 20739 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_128rows Geometries: 65237 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 5290 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 37638 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 11396 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 35074 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 10255431 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 594 Checks: 167 Errors: 0
ERROR: file calibre.py: line 131: sram_1rw_64b_1024w_2bank_freepdk45 Geometries: 20550242 Checks: 167 Errors: 1
ERROR: file design.py: line 87: DRC failed for sram_1rw_64b_1024w_2bank_freepdk45

86
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_16936_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_1024w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_16936_temp/ =========|
|==============================================================================|
Output files are sram_1rw_8b_1024w_4bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 8
Words: 1024
Banks: 4
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 22:05:07.033164 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 13 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3983 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 5321 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 8875 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 64 x 32
[verify.calibre/run_drc]: bitcell_array Geometries: 622818 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 5570 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 3029 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 1987 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 2595 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 34473 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4703 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 4710 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1428 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 17538 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 713631 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 1181 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_8b_1024w_4bank_freepdk45 Geometries: 3116996 Checks: 167 Errors: 0
** SRAM creation: 155.1 seconds
SP: Writing to ./sram_1rw_8b_1024w_4bank_freepdk45.sp
** Spice writing: 0.0 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_1024w_4bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_16936_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 1111111111 address
[characterizer.trim_spice/trim]: Keeping 7 data bit
[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
ERROR: file delay.py: line 309: Timed out, could not find a feasible period.

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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_17125_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_256w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_17125_temp/ =========|
|==============================================================================|
Output files are sram_1rw_8b_256w_1bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 8
Words: 256
Banks: 1
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 06:07:13.473469 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 13 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 3983 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 5321 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 8875 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 64 x 32
[verify.calibre/run_drc]: bitcell_array Geometries: 622818 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 5570 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 3029 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 1987 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 2595 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_64rows Geometries: 34473 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4703 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 4710 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1428 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 17538 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 711403 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_8b_256w_1bank_freepdk45 Geometries: 722780 Checks: 167 Errors: 0
** SRAM creation: 147.1 seconds
SP: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.sp
** Spice writing: 0.0 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_256w_1bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_17125_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 11111111 address
[characterizer.trim_spice/trim]: Keeping 7 data bit
[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[63] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 0.56986783ns/0.10418749ns slew 0.031200233ns/0.040857947ns
[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 0.625ns (ub: 1.25 lb: 0.0)
[characterizer.delay/find_min_period]: MinPeriod Search: 0.9375ns (ub: 1.25 lb: 0.625)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.09375ns (ub: 1.25 lb: 0.9375)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.015625ns (ub: 1.09375 lb: 0.9375)
[characterizer.delay/find_min_period]: MinPeriod Search: 1.0546875ns (ub: 1.09375 lb: 1.015625)
[characterizer.delay/analyze]: Min Period: 1.0546875n with a delay of 0.56986783 / 0.10418749
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953
[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437
[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094
[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141
** Characterization: 3369.3 seconds
GDS: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.gds
** GDS: 0.8 seconds
LEF: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.lef
** LEF: 2.0 seconds
Verilog: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.v
** Verilog: 0.0 seconds
** End: 3520.0 seconds

86
lib/freepdk45/sram_1rw_8b_512w_1bank_freepdk45.log Normal file
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_21736_temp/
[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_512w_1bank_freepdk45.py
[globals/read_config]: Output saved in ./
[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
|==============================================================================|
|========= OpenRAM Compiler =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= University of California Santa Cruz CE Department =========|
|========= =========|
|========= VLSI Computer Architecture Research Group =========|
|========= Oklahoma State University ECE Department =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= Temp dir: /tmp/openram_mrg_21736_temp/ =========|
|==============================================================================|
Output files are sram_1rw_8b_512w_4bank_freepdk45.(sp|gds|v|lib|lef)
Technology: freepdk45
Word size: 8
Words: 512
Banks: 4
[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
** Start: 2018-02-24 05:27:47.667578 seconds
[sram/compute_sizes]: Words per row: 4
[control_logic/__init__]: Creating control_logic
[ms_flop_array/__init__]: Creating msf_control
[verify.calibre/run_drc]: msf_control Geometries: 1768 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitline_load 7 x 1
[verify.calibre/run_drc]: bitline_load Geometries: 2147 Checks: 167 Errors: 0
[verify.calibre/run_drc]: delay_chain Geometries: 906 Checks: 167 Errors: 0
[verify.calibre/run_drc]: replica_bitline Geometries: 3446 Checks: 167 Errors: 0
[verify.calibre/run_drc]: control_logic Geometries: 6991 Checks: 167 Errors: 0
[bitcell_array/__init__]: Creating bitcell_array 32 x 32
[verify.calibre/run_drc]: bitcell_array Geometries: 311458 Checks: 167 Errors: 0
[precharge_array/__init__]: Creating precharge_array
[verify.calibre/run_drc]: precharge Geometries: 86 Checks: 167 Errors: 0
[verify.calibre/run_drc]: precharge_array Geometries: 5570 Checks: 167 Errors: 0
[single_level_column_mux_array/__init__]: Creating columnmux_array
[verify.calibre/run_drc]: columnmux_array Geometries: 3029 Checks: 167 Errors: 0
[sense_amp_array/__init__]: Creating sense_amp_array
[verify.calibre/run_drc]: sense_amp_array Geometries: 1987 Checks: 167 Errors: 0
[write_driver_array/__init__]: Creating write_driver_array
[verify.calibre/run_drc]: write_driver_array Geometries: 2595 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre2x4 Geometries: 969 Checks: 167 Errors: 0
[verify.calibre/run_drc]: pre3x8 Geometries: 2251 Checks: 167 Errors: 0
[verify.calibre/run_drc]: hierarchical_decoder_32rows Geometries: 9834 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_address
[verify.calibre/run_drc]: msf_address Geometries: 4116 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msf_data_in
[verify.calibre/run_drc]: msf_data_in Geometries: 4710 Checks: 167 Errors: 0
[tri_gate_array/__init__]: Creating tri_gate_array
[verify.calibre/run_drc]: tri_gate_array Geometries: 1428 Checks: 167 Errors: 0
[verify.calibre/run_drc]: wordline_driver Geometries: 8770 Checks: 167 Errors: 0
[verify.calibre/run_drc]: bank Geometries: 366234 Checks: 167 Errors: 0
[ms_flop_array/__init__]: Creating msb_address
[verify.calibre/run_drc]: msb_address Geometries: 1181 Checks: 167 Errors: 0
[verify.calibre/run_drc]: sram_1rw_8b_512w_4bank_freepdk45 Geometries: 1621777 Checks: 167 Errors: 0
** SRAM creation: 151.4 seconds
SP: Writing to ./sram_1rw_8b_512w_4bank_freepdk45.sp
** Spice writing: 0.0 seconds
[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
LIB: Characterizing...
Performing simulation-based characterization with xa
Trimming netlist to speed up characterization.
[characterizer.lib/prepare_tables]: Loads: [ 0.052275 0.2091 1.6728 ]
[characterizer.lib/prepare_tables]: Slews: [ 0.00125 0.005 0.04 ]
[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_512w_4bank_freepdk45_TT_1p0V_25C.lib
[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_21736_temp/reduced.sp.
[characterizer.trim_spice/trim]: Keeping 111111111 address
[characterizer.trim_spice/trim]: Keeping 7 data bit
[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
[characterizer.trim_spice/trim]: Keeping wl[127] (trimming other WLs)
[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
ERROR: file delay.py: line 309: Timed out, could not find a feasible period.

47
lib/freepdk45/verilog/sram_1rw_128b_1024w_1bank_freepdk45.v Normal file
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// OpenRAM SRAM model
// Words: 1024
// Word size: 128
module sram_1rw_128b_1024w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
parameter DATA_WIDTH = 128 ;
parameter ADDR_WIDTH = 10 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
parameter DELAY = 3 ;
inout [DATA_WIDTH-1:0] DATA;
input [ADDR_WIDTH-1:0] ADDR;
input CSb; // active low chip select
input WEb; // active low write control
input OEb; // active output enable
input clk; // clock
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Tri-State Buffer control
// output : When WEb = 1, oeb = 0, csb = 0
assign DATA = (!CSb && !OEb && WEb) ? data_out : 128'bz;
// Memory Write Block
// Write Operation : When WEb = 0, CSb = 0
always @ (posedge clk)
begin : MEM_WRITE
if ( !CSb && !WEb ) begin
mem[ADDR] = DATA;
$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
end
end
// Memory Read Block
// Read Operation : When WEb = 1, CSb = 0
always @ (posedge clk)
begin : MEM_READ
if (!CSb && WEb) begin
data_out <= #(DELAY) mem[ADDR];
$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
end
end
endmodule

47
lib/freepdk45/verilog/sram_1rw_128b_1024w_4bank_freepdk45.v Normal file
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// OpenRAM SRAM model
// Words: 1024
// Word size: 128
module sram_1rw_128b_1024w_4bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
parameter DATA_WIDTH = 128 ;
parameter ADDR_WIDTH = 10 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
parameter DELAY = 3 ;
inout [DATA_WIDTH-1:0] DATA;
input [ADDR_WIDTH-1:0] ADDR;
input CSb; // active low chip select
input WEb; // active low write control
input OEb; // active output enable
input clk; // clock
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Tri-State Buffer control
// output : When WEb = 1, oeb = 0, csb = 0
assign DATA = (!CSb && !OEb && WEb) ? data_out : 128'bz;
// Memory Write Block
// Write Operation : When WEb = 0, CSb = 0
always @ (posedge clk)
begin : MEM_WRITE
if ( !CSb && !WEb ) begin
mem[ADDR] = DATA;
$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
end
end
// Memory Read Block
// Read Operation : When WEb = 1, CSb = 0
always @ (posedge clk)
begin : MEM_READ
if (!CSb && WEb) begin
data_out <= #(DELAY) mem[ADDR];
$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
end
end
endmodule

47
lib/freepdk45/verilog/sram_1rw_32b_1024w_1bank_freepdk45.v Normal file
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// OpenRAM SRAM model
// Words: 1024
// Word size: 32
module sram_1rw_32b_1024w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
parameter DATA_WIDTH = 32 ;
parameter ADDR_WIDTH = 10 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
parameter DELAY = 3 ;
inout [DATA_WIDTH-1:0] DATA;
input [ADDR_WIDTH-1:0] ADDR;
input CSb; // active low chip select
input WEb; // active low write control
input OEb; // active output enable
input clk; // clock
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Tri-State Buffer control
// output : When WEb = 1, oeb = 0, csb = 0
assign DATA = (!CSb && !OEb && WEb) ? data_out : 32'bz;
// Memory Write Block
// Write Operation : When WEb = 0, CSb = 0
always @ (posedge clk)
begin : MEM_WRITE
if ( !CSb && !WEb ) begin
mem[ADDR] = DATA;
$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
end
end
// Memory Read Block
// Read Operation : When WEb = 1, CSb = 0
always @ (posedge clk)
begin : MEM_READ
if (!CSb && WEb) begin
data_out <= #(DELAY) mem[ADDR];
$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
end
end
endmodule

47
lib/freepdk45/verilog/sram_1rw_32b_2048w_1bank_freepdk45.v Normal file
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// OpenRAM SRAM model
// Words: 2048
// Word size: 32
module sram_1rw_32b_2048w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
parameter DATA_WIDTH = 32 ;
parameter ADDR_WIDTH = 11 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
parameter DELAY = 3 ;
inout [DATA_WIDTH-1:0] DATA;
input [ADDR_WIDTH-1:0] ADDR;
input CSb; // active low chip select
input WEb; // active low write control
input OEb; // active output enable
input clk; // clock
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Tri-State Buffer control
// output : When WEb = 1, oeb = 0, csb = 0
assign DATA = (!CSb && !OEb && WEb) ? data_out : 32'bz;
// Memory Write Block
// Write Operation : When WEb = 0, CSb = 0
always @ (posedge clk)
begin : MEM_WRITE
if ( !CSb && !WEb ) begin
mem[ADDR] = DATA;
$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
end
end
// Memory Read Block
// Read Operation : When WEb = 1, CSb = 0
always @ (posedge clk)
begin : MEM_READ
if (!CSb && WEb) begin
data_out <= #(DELAY) mem[ADDR];
$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
end
end
endmodule

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