Merge branch 'tech_migration' into dev

compiler/base/contact.py

@@ -65,8 +65,10 @@ class contact(hierarchy_design.hierarchy_design):
         self.create_second_layer_enclosure()
         self.create_nitride_cut_enclosure()
         
-        self.height = max(obj.offset.y + obj.height for obj in self.objs)
+        self.height = max(self.first_layer_position.y + self.first_layer_height,
-        self.width = max(obj.offset.x + obj.width for obj in self.objs)
+                          self.second_layer_position.y + self.second_layer_height)
+        self.width = max(self.first_layer_position.x + self.first_layer_width,
+                         self.second_layer_position.x + self.second_layer_width)
 
         # Do not include the select layer in the height/width
         if self.implant_type and self.well_type:
@@ -83,7 +85,7 @@ class contact(hierarchy_design.hierarchy_design):
         self.second_layer_name = second_layer
         
         # Contacts will have unique per first layer
-        if via_layer in tech.layer.keys():
+        if via_layer in tech.layer:
             self.via_layer_name = via_layer
         elif via_layer == "contact":
             if first_layer in ("active", "poly"):
@@ -171,7 +173,7 @@ class contact(hierarchy_design.hierarchy_design):
     def create_nitride_cut_enclosure(self):
         """ Special layer that encloses poly contacts in some processes """
         # Check if there is a special poly nitride cut layer
-        if "npc" not in tech.layer.keys():
+        if "npc" not in tech.layer:
             return
 
         # Only add for poly layers
@@ -224,13 +226,18 @@ class contact(hierarchy_design.hierarchy_design):
                       offset=implant_position,
                       width=implant_width,
                       height=implant_height)
-        well_position = self.first_layer_position - [drc("well_enclose_active")] * 2
+
-        well_width = self.first_layer_width + 2 * drc("well_enclose_active")
+        # Optionally implant well if layer exists
-        well_height = self.first_layer_height + 2 * drc("well_enclose_active")
+        well_layer = "{}well".format(self.well_type)
-        self.add_rect(layer="{}well".format(self.well_type),
+        if well_layer in tech.layer:
-                      offset=well_position,
+            well_enclose_active = drc(well_layer + "_enclose_active")
-                      width=well_width,
+            well_position = self.first_layer_position - [well_enclose_active] * 2
-                      height=well_height)
+            well_width = self.first_layer_width + 2 * well_enclose_active
+            well_height = self.first_layer_height + 2 * well_enclose_active
+            self.add_rect(layer=well_layer,
+                          offset=well_position,
+                          width=well_width,
+                          height=well_height)
         
     def analytical_power(self, corner, load):
         """ Get total power of a module  """

compiler/base/design.py

@@ -63,8 +63,8 @@ class design(hierarchy_design):
 
         contact1 = getattr(contact, layer1 + layer2)
         max_contact = max(contact1.width, contact1.height)
-        layer1_space = getattr(self, layer1+"_space")
+        layer1_space = getattr(self, layer1 + "_space")
-        layer2_space = getattr(self, layer2+"_space")
+        layer2_space = getattr(self, layer2 + "_space")
         pitch = max_contact + max(layer1_space, layer2_space)
 
         return pitch
@@ -83,7 +83,7 @@ class design(hierarchy_design):
                 if match.group(1) == "active_contact":
                     setattr(self, "contact_width", drc(match.group(0)))
                 else:
-                    setattr(self, match.group(1)+"_width", drc(match.group(0)))
+                    setattr(self, match.group(1) + "_width", drc(match.group(0)))
 
             # Single layer area rules
             match = re.search(r"minarea_(.*)", rule)
@@ -93,10 +93,10 @@ class design(hierarchy_design):
             # Single layer spacing rules
             match = re.search(r"(.*)_to_(.*)", rule)
             if match and match.group(1) == match.group(2):
-                setattr(self, match.group(1)+"_space", drc(match.group(0)))
+                setattr(self, match.group(1) + "_space", drc(match.group(0)))
             elif match and match.group(1) != match.group(2):
                 if match.group(2) == "poly_active":
-                    setattr(self, match.group(1)+"_to_contact",
+                    setattr(self, match.group(1) + "_to_contact",
                             drc(match.group(0)))
                 else:
                     setattr(self, match.group(0), drc(match.group(0)))

compiler/base/geometry.py

@@ -69,7 +69,9 @@ class geometry:
         """ Transform with offset, mirror and rotation to get the absolute pin location.
         We must then re-find the ll and ur. The master is the cell instance. """
         if OPTS.netlist_only:
+            self.boundary = [vector(0,0), vector(0,0)]
             return
+        
         (ll, ur) = [vector(0, 0), vector(self.width, self.height)]
 
         if mirror == "MX":

compiler/base/pin_layout.py

@@ -129,6 +129,13 @@ class pin_layout:
 
         self.rect = [vector(min_x, min_y), vector(max_x, max_y)]
         
+    def fix_minarea(self):
+        """
+        Try to fix minimum area rule.
+        """
+        min_area = drc("{}_minarea".format(self.layer))
+        pass
+    
     def inflate(self, spacing=None):
         """
         Inflate the rectangle by the spacing (or other rule)

compiler/bitcells/pbitcell.py

@@ -977,33 +977,36 @@ class pbitcell(bitcell_base.bitcell_base):
         """
         # extend pwell to encompass entire nmos region of the cell up to the
         # height of the tallest nmos transistor
-        max_nmos_well_height = max(self.inverter_nmos.cell_well_height,
+        max_nmos_well_height = max(self.inverter_nmos.well_height,
-                                   self.readwrite_nmos.cell_well_height,
+                                   self.readwrite_nmos.well_height,
-                                   self.write_nmos.cell_well_height,
+                                   self.write_nmos.well_height,
-                                   self.read_nmos.cell_well_height)
+                                   self.read_nmos.well_height)
         well_height = max_nmos_well_height + self.port_ypos \
-                      - self.well_enclose_active - self.gnd_position.y
+                      - self.nwell_enclose_active - self.gnd_position.y
-        offset = vector(self.leftmost_xpos, self.botmost_ypos)
+        # FIXME fudge factor xpos
+        well_width = self.width + 2*self.nwell_enclose_active
+        offset = vector(self.leftmost_xpos - self.nwell_enclose_active, self.botmost_ypos)
         self.add_rect(layer="pwell",
                       offset=offset,
-                      width=self.width,
+                      width=well_width,
                       height=well_height)
 
         # extend nwell to encompass inverter_pmos
         # calculate offset of the left pmos well
         inverter_well_xpos = -(self.inverter_nmos.active_width + 0.5 * self.inverter_to_inverter_spacing) \
-                             - self.well_enclose_active
+                             - self.nwell_enclose_active
         inverter_well_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \
-                             + self.inverter_gap - self.well_enclose_active
+                             + self.inverter_gap - self.nwell_enclose_active
 
         # calculate width of the two combined nwells
         # calculate height to encompass nimplant connected to vdd
         well_width = 2 * (self.inverter_nmos.active_width + 0.5 * self.inverter_to_inverter_spacing) \
-                     + 2 * self.well_enclose_active
+                     + 2 * self.nwell_enclose_active
         well_height = self.vdd_position.y - inverter_well_ypos \
-                      + self.well_enclose_active + drc["minwidth_tx"]
+                      + self.nwell_enclose_active + drc["minwidth_tx"]
 
-        offset = [inverter_well_xpos, inverter_well_ypos]
+        # FIXME fudge factor xpos
+        offset = [inverter_well_xpos + 2*self.nwell_enclose_active, inverter_well_ypos]
         self.add_rect(layer="nwell",
                       offset=offset,
                       width=well_width,

compiler/modules/bank.py

@@ -333,7 +333,7 @@ class bank(design.design):
         self.col_addr_bus_width = self.m2_pitch*self.num_col_addr_lines
 
         # A space for wells or jogging m2
-        self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"),
+        self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"),
                           3*self.m2_pitch)
 
 

compiler/modules/port_address.py

@@ -149,7 +149,7 @@ class port_address(design.design):
         """
 
         # A space for wells or jogging m2
-        self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"),
+        self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"),
                           3*self.m2_pitch)
         
         row_decoder_offset = vector(0,0)

compiler/modules/port_data.py

@@ -212,7 +212,7 @@ class port_data(design.design):
 
 
         # A space for wells or jogging m2 between modules
-        self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"),
+        self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"),
                           3*self.m2_pitch)
 
 

compiler/pgates/pgate.py

@@ -8,7 +8,7 @@
 import contact
 import design
 import debug
-from tech import layer, drc
+from tech import layer
 from vector import vector
 from globals import OPTS
 from sram_factory import factory
@@ -126,29 +126,35 @@ class pgate(design.design):
     def extend_wells(self, middle_position):
         """ Extend the n/p wells to cover whole cell """
 
+        # FIXME: float rounding problem
+        middle_position = middle_position.snap_to_grid()
         # Add a rail width to extend the well to the top of the rail
-        max_y_offset = self.height + 0.5 * self.m1_width
+        nwell_max_offset = max(self.find_highest_layer_coords("nwell").y,
-        self.nwell_position = middle_position
+                               self.height + 0.5 * self.m1_width)
-        nwell_height = max_y_offset - middle_position.y
+        nwell_position = middle_position
-        if layer["nwell"]:
+        nwell_height = nwell_max_offset - middle_position.y
+        if "nwell" in layer:
             self.add_rect(layer="nwell",
                           offset=middle_position,
                           width=self.well_width,
                           height=nwell_height)
-        if layer["vtg"]:
+        if "vtg" in layer:
             self.add_rect(layer="vtg",
-                          offset=self.nwell_position,
+                          offset=nwell_position,
                           width=self.well_width,
                           height=nwell_height)
 
-        pwell_position = vector(0, -0.5 * self.m1_width)
+        # Start this half a rail width below the cell
+        pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y,
+                               -0.5 * self.m1_width)
+        pwell_position = vector(0, pwell_min_offset)
         pwell_height = middle_position.y - pwell_position.y
-        if layer["pwell"]:
+        if "pwell" in layer:
             self.add_rect(layer="pwell",
                           offset=pwell_position,
                           width=self.well_width,
                           height=pwell_height)
-        if layer["vtg"]:
+        if "vtg" in layer:
             self.add_rect(layer="vtg",
                           offset=pwell_position,
                           width=self.well_width,
@@ -168,7 +174,7 @@ class pgate(design.design):
         # OR align the active with the top of PMOS active.
         max_y_offset = self.height + 0.5 * self.m1_width
         contact_yoffset = min(pmos_pos.y + pmos.active_height - pmos.active_contact.first_layer_height,
-                              max_y_offset - pmos.active_contact.first_layer_height / 2 - self.well_enclose_active)
+                              max_y_offset - pmos.active_contact.first_layer_height / 2 - self.nwell_enclose_active)
         contact_offset = vector(contact_xoffset, contact_yoffset)
         # Offset by half a contact in x and y
         contact_offset += vector(0.5 * pmos.active_contact.first_layer_width,
@@ -220,7 +226,7 @@ class pgate(design.design):
         # Must be at least an well enclosure of active up
         # from the bottom of the well
         contact_yoffset = max(nmos_pos.y,
-                              self.well_enclose_active \
+                              self.nwell_enclose_active \
                               - nmos.active_contact.first_layer_height / 2)
         contact_offset = vector(contact_xoffset, contact_yoffset)
 

compiler/pgates/pinv.py

@@ -153,7 +153,7 @@ class pinv(pgate.pgate):
         # the well width is determined the multi-finger PMOS device width plus
         # the well contact width and half well enclosure on both sides
         self.well_width = self.pmos.active_width + self.pmos.active_contact.width \
-                          + self.active_space + 2*self.well_enclose_active
+                          + self.active_space + 2*self.nwell_enclose_active
         self.width = self.well_width
         # Height is an input parameter, so it is not recomputed.
         
@@ -223,7 +223,7 @@ class pinv(pgate.pgate):
         self.output_pos = vector(0, 0.5 * (pmos_drain_pos.y + nmos_drain_pos.y))
 
         # This will help with the wells
-        self.well_pos = vector(0, self.nmos_inst.uy())
+        self.well_pos = self.output_pos
 
     def route_outputs(self):
         """

compiler/pgates/pnand2.py

@@ -100,7 +100,7 @@ class pnand2(pgate.pgate):
         # Enclosure space on the sides.
         self.well_width = 2 * self.pmos.active_width + contact.activem1.width \
                           + 2 * self.active_space \
-                          + 2 * self.well_enclose_active
+                          + 2 * self.nwell_enclose_active
 
         self.width = self.well_width
         # Height is an input parameter, so it is not recomputed.
@@ -171,7 +171,7 @@ class pnand2(pgate.pgate):
                                  0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height))
 
         # This will help with the wells
-        self.well_pos = vector(0, self.nmos1_inst.uy())
+        self.well_pos = self.output_pos
         
     def add_well_contacts(self):
         """ 

compiler/pgates/pnand3.py

@@ -92,14 +92,11 @@ class pnand3(pgate.pgate):
         # Two PMOS devices and a well contact. Separation between each.
         # Enclosure space on the sides.
         self.well_width = 3 * self.pmos.active_width + self.pmos.active_contact.width \
-                          + 2 * self.active_space + 2 * self.well_enclose_active \
+                          + 2 * self.active_space + 2 * self.nwell_enclose_active \
                           - self.overlap_offset.x
         self.width = self.well_width
         # Height is an input parameter, so it is not recomputed.
 
-        # This will help with the wells and the input/output placement
-        self.output_pos = vector(0, 0.5*self.height)
-
         # This is the extra space needed to ensure DRC rules
         # to the active contacts
         nmos = factory.create(module_type="ptx", tx_type="nmos")
@@ -179,8 +176,11 @@ class pnand3(pgate.pgate):
         self.nmos3_pos = nmos2_pos + self.overlap_offset
         self.nmos3_inst.place(self.nmos3_pos)
 
+        # This will help with the wells and the input/output placement
+        self.output_pos = vector(0, 0.5*self.height)
+
         # This should be placed at the top of the NMOS well
-        self.well_pos = vector(0, self.nmos1_inst.uy())
+        self.well_pos = self.output_pos
         
     def add_well_contacts(self):
         """ Add n/p well taps to the layout and connect to supplies """

compiler/pgates/pnor2.py

@@ -98,7 +98,7 @@ class pnor2(pgate.pgate):
         self.well_width = 2 * self.pmos.active_width \
                           + self.pmos.active_contact.width \
                           + 2 * self.active_space \
-                          + 2 * self.well_enclose_active
+                          + 2 * self.nwell_enclose_active
         self.width = self.well_width
         # Height is an input parameter, so it is not recomputed.
 
@@ -136,7 +136,6 @@ class pnor2(pgate.pgate):
                                         mod=self.pmos)
         self.connect_inst(["net1", "B", "Z", "vdd"])
 
-        
         self.nmos1_inst = self.add_inst(name="pnor2_nmos1",
                                         mod=self.nmos)
         self.connect_inst(["Z", "A", "gnd", "gnd"])
@@ -170,7 +169,7 @@ class pnor2(pgate.pgate):
                                  0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height))
 
         # This will help with the wells
-        self.well_pos = vector(0, self.nmos1_inst.uy())
+        self.well_pos = self.output_pos
         
     def add_well_contacts(self):
         """ Add n/p well taps to the layout and connect to supplies """

compiler/pgates/precharge.py

@@ -116,7 +116,7 @@ class precharge(design.design):
         # adds the lower pmos to layout
         bl_xoffset = self.bitcell.get_pin(self.bitcell_bl).lx()
         self.lower_pmos_position = vector(max(bl_xoffset - contact_xdiff,
-                                              self.well_enclose_active),
+                                              self.nwell_enclose_active),
                                           self.pmos.active_offset.y)
         self.lower_pmos_inst.place(self.lower_pmos_position)
 
@@ -176,7 +176,7 @@ class precharge(design.design):
         # adds the contact from active to metal1
         well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \
                            + vector(0, self.upper_pmos1_inst.uy() + contact.activem1.height / 2 \
-                                    + self.well_extend_active)
+                                    + self.nwell_extend_active)
         self.add_via_center(layers=self.active_stack,
                             offset=well_contact_pos,
                             implant_type="n",

compiler/pgates/ptristate_inv.py

@@ -61,7 +61,6 @@ class ptristate_inv(pgate.pgate):
         """ Adds pins for spice netlist """
         self.add_pin_list(["in", "out", "en", "en_bar", "vdd", "gnd"])
 
-
     def setup_layout_constants(self):
         """
         Pre-compute some handy layout parameters.
@@ -73,7 +72,7 @@ class ptristate_inv(pgate.pgate):
 
         # Two PMOS devices and a well contact. Separation between each.
         # Enclosure space on the sides.
-        self.well_width = 2 * self.pmos.active_width + self.well_enclose_active
+        self.well_width = 2 * self.pmos.active_width + self.nwell_enclose_active
 
         # Add an extra space because we route the output on the right of the S/D
         self.width = self.well_width + 0.5 * self.m1_space
@@ -82,7 +81,6 @@ class ptristate_inv(pgate.pgate):
         # Make sure we can put a well above and below
         self.top_bottom_space = max(contact.activem1.width, contact.activem1.height)
         
-        
     def add_ptx(self):
         """ Create the PMOS and NMOS transistors. """
         self.nmos = factory.create(module_type="ptx",
@@ -95,7 +93,6 @@ class ptristate_inv(pgate.pgate):
                                    width=self.pmos_width,
                                    mults=1,
                                    tx_type="pmos")
-
         self.add_mod(self.pmos)
         
     def route_supply_rails(self):

compiler/pgates/ptx.py

@@ -58,11 +58,11 @@ class ptx(design.design):
         # some transistor sizes in other netlist depend on pbitcell
         self.create_layout()
 
-        #ll = self.find_lowest_coords()
+        ll = self.find_lowest_coords()
-        #ur = self.find_highest_coords()
+        ur = self.find_highest_coords()
-        #self.add_boundary(ll, ur)
+        self.add_boundary(ll, ur)
 
-        # (0,0) will be the corner ofthe active area (not the larger well)
+        # (0,0) will be the corner of the active area (not the larger well)
         self.translate_all(self.active_offset)
         
     def create_layout(self):
@@ -99,7 +99,7 @@ class ptx(design.design):
                                                                   drc("minwidth_poly"))
         area_str = "pd={0:.2f}u ps={0:.2f}u as={1:.2f}p ad={1:.2f}p".format(perimeter_sd,
                                                                             area_sd)
-        self.spice_device= main_str + area_str
+        self.spice_device = main_str + area_str
         self.spice.append("\n* ptx " + self.spice_device)
         # self.spice.append(".ENDS {0}".format(self.name))
 
@@ -108,8 +108,8 @@ class ptx(design.design):
         Pre-compute some handy layout parameters.
         """
 
-        if self.num_contacts==None:
+        if not self.num_contacts:
-            self.num_contacts=self.calculate_num_contacts()
+            self.num_contacts = self.calculate_num_contacts()
 
         # Determine layer types needed
         if self.tx_type == "nmos":
@@ -119,34 +119,35 @@ class ptx(design.design):
             self.implant_type = "p"
             self.well_type = "n"
         else:
-            self.error("Invalid transitor type.",-1)
+            self.error("Invalid transitor type.", -1)
-            
             
         # This is not actually instantiated but used for calculations
         self.active_contact = factory.create(module_type="contact",
                                              layer_stack=self.active_stack,
-                                             directions = ("V", "V"),
+                                             directions=("V", "V"),
                                              dimensions=(1, self.num_contacts))
 
-        
+        # The contacted poly pitch
-        # The contacted poly pitch (or uncontacted in an odd technology)
         self.poly_pitch = max(2 * self.contact_to_gate + self.contact_width + self.poly_width,
                               self.poly_space)
 
-        # The contacted poly pitch (or uncontacted in an odd technology)
+        # The contacted poly pitch
-        self.contact_pitch = 2 * self.contact_to_gate + self.contact_width + self.poly_width
+        self.contact_spacing = 2 * self.contact_to_gate + \
+                               self.contact_width + self.poly_width
 
-        # The enclosure of an active contact. Not sure about second term.
+        # This is measured because of asymmetric enclosure rules
-        active_enclose_contact = max(self.active_enclose_contact,
+        active_enclose_contact = 0.5*(self.active_contact.width - self.contact_width)
-                                     (self.active_width - self.contact_width) / 2)
-                                                                  
-        # This is the distance from the edge of poly to the contacted end of active
-        self.end_to_poly = active_enclose_contact + self.contact_width + self.contact_to_gate
         
+        # This is the distance from the side of
+        # poly gate to the contacted end of active
+        # (i.e. the "outside" contacted diffusion sizes)
+        self.end_to_poly = self.active_contact.width - active_enclose_contact + \
+                           self.contact_to_gate
         
         # Active width is determined by enclosure on both ends and contacted pitch,
         # at least one poly and n-1 poly pitches
-        self.active_width = 2 * self.end_to_poly + self.poly_width + (self.mults - 1) * self.poly_pitch
+        self.active_width = 2 * self.end_to_poly + self.poly_width + \
+                                 (self.mults - 1) * self.poly_pitch
 
         # Active height is just the transistor width
         self.active_height = self.tx_width
@@ -154,32 +155,35 @@ class ptx(design.design):
         # Poly height must include poly extension over active
         self.poly_height = self.tx_width + 2 * self.poly_extend_active
 
+        well_name = "{}well".format(self.well_type)
+        
         # The active offset is due to the well extension
-        self.active_offset = vector([self.well_enclose_active] * 2)
+        if well_name in layer:
+            well_enclose_active = drc(well_name + "_enclose_active")
+            self.active_offset = vector([well_enclose_active] * 2)
+        else:
+            self.active_offset = vector(0, 0)
 
         # Well enclosure of active, ensure minwidth as well
-        well_name = "{}well".format(self.well_type)
+        if well_name in layer:
-        if layer[well_name]:
+            well_width_rule = drc("minwidth_" + well_name)
-            self.cell_well_width = max(self.active_width + 2 * self.well_enclose_active,
+            well_enclose_active = drc(well_name + "_enclose_active")
-                                       self.well_width)
+            self.well_width = max(self.active_width + 2 * well_enclose_active,
-            self.cell_well_height = max(self.tx_width + 2 * self.well_enclose_active,
+                                  well_width_rule)
-                                        self.well_width)
+            self.well_height = max(self.active_height + 2 * well_enclose_active,
+                                   well_width_rule)
             # We are going to shift the 0,0, so include that in the width and height
-            self.height = self.cell_well_height - self.active_offset.y
+            self.height = self.well_height - self.active_offset.y
-            self.width = self.cell_well_width - self.active_offset.x
+            self.width = self.well_width - self.active_offset.x
         else:
-            # If no well, use the boundary of the active and poly
+            # The well is not included in the height and width
             self.height = self.poly_height
             self.width = self.active_width
         
-        # The active offset is due to the well extension
-        self.active_offset = vector([self.well_enclose_active] * 2)
-
         # This is the center of the first active contact offset (centered vertically)
-        self.contact_offset = self.active_offset + vector(active_enclose_contact + 0.5 * self.contact_width,
+        self.contact_offset = self.active_offset + vector(0.5 * self.active_contact.width,
                                                           0.5 * self.active_height)
                                      
-        
         # Min area results are just flagged for now.
         debug.check(self.active_width * self.active_height >= self.minarea_active,
                     "Minimum active area violated.")
@@ -215,14 +219,14 @@ class ptx(design.design):
             poly_offset = poly_positions[0] + vector(-0.5 * self.poly_width,
                                                      distance_above_active)
         # Remove the old pin and add the new one
-        self.remove_layout_pin("G") # only keep the main pin
+        # only keep the main pin
+        self.remove_layout_pin("G")
         self.add_layout_pin(text="G",
                             layer="poly",
                             offset=poly_offset,
                             width=poly_width,
                             height=self.poly_width)
 
-
     def connect_fingered_active(self, drain_positions, source_positions):
         """
         Connect each contact  up/down to a source or drain pin
@@ -230,10 +234,10 @@ class ptx(design.design):
         
         # This is the distance that we must route up or down from the center
         # of the contacts to avoid DRC violations to the other contacts
-        pin_offset = vector(0, 0.5 * self.active_contact.second_layer_height \
+        pin_offset = vector(0,
-                            + self.m1_space + 0.5 * self.m1_width)
+                            0.5 * self.active_contact.second_layer_height + self.m1_space + 0.5 * self.m1_width)
         # This is the width of a m1 extend the ends of the pin
-        end_offset = vector(self.m1_width/2,0)
+        end_offset = vector(self.m1_width / 2.0, 0)
 
         # drains always go to the MIDDLE of the cell,
         # so top of NMOS, bottom of PMOS
@@ -246,8 +250,9 @@ class ptx(design.design):
             source_dir = -1
             
         if len(source_positions) > 1:
-            source_offset = pin_offset.scale(source_dir,source_dir)
+            source_offset = pin_offset.scale(source_dir, source_dir)
-            self.remove_layout_pin("S") # remove the individual connections
+            # remove the individual connections
+            self.remove_layout_pin("S")
             # Add each vertical segment
             for a in source_positions:
                 self.add_path(("m1"),
@@ -326,17 +331,26 @@ class ptx(design.design):
         Add an (optional) well and implant for the type of transistor.
         """
         well_name = "{}well".format(self.well_type)
-        if layer[well_name]:
+        if not (well_name in layer or "vtg" in layer):
-            self.add_rect(layer=well_name,
+            return
-                          offset=(0,0),
-                          width=self.cell_well_width,
-                          height=self.cell_well_height)
-        if layer["vtg"]:
-            self.add_rect(layer="vtg",
-                          offset=(0,0),
-                          width=self.cell_well_width,
-                          height=self.cell_well_height)
 
+        center_pos = self.active_offset + vector(self.width / 2.0,
+                                                 self.height / 2.0)
+        well_ll = center_pos - vector(self.well_width / 2.0,
+                                      self.well_height / 2.0)
+        well_ll = well_ll - vector(0,
+                                   self.poly_extend_active)
+            
+        if well_name in layer:
+            self.add_rect(layer=well_name,
+                          offset=well_ll,
+                          width=self.well_width,
+                          height=self.well_height)
+        if "vtg" in layer:
+            self.add_rect(layer="vtg",
+                          offset=well_ll,
+                          width=self.well_width,
+                          height=self.well_height)
 
     def calculate_num_contacts(self):
         """
@@ -345,7 +359,6 @@ class ptx(design.design):
         """
         return 1
 
-
     def get_contact_positions(self):
         """
         Create a list of the centers of drain and source contact positions.
@@ -359,10 +372,10 @@ class ptx(design.design):
         for i in range(self.mults):
             if i%2:
                 # It's a source... so offset from previous drain.
-                source_positions.append(drain_positions[-1] + vector(self.contact_pitch, 0))
+                source_positions.append(drain_positions[-1] + vector(self.contact_spacing, 0))
             else:
                 # It's a drain... so offset from previous source.
-                drain_positions.append(source_positions[-1] + vector(self.contact_pitch, 0))
+                drain_positions.append(source_positions[-1] + vector(self.contact_spacing, 0))
 
         return [source_positions,drain_positions]
         
@@ -377,7 +390,7 @@ class ptx(design.design):
             contact=self.add_via_center(layers=self.active_stack,
                                         offset=pos,
                                         size=(1, self.num_contacts),
-                                        directions=("H","V"),
+                                        directions=("V","V"),
                                         implant_type=self.implant_type,
                                         well_type=self.well_type)
             self.add_layout_pin_rect_center(text="S",
@@ -391,7 +404,7 @@ class ptx(design.design):
             contact=self.add_via_center(layers=self.active_stack,
                                         offset=pos,
                                         size=(1, self.num_contacts),
-                                        directions=("H","V"),
+                                        directions=("V","V"),
                                         implant_type=self.implant_type,
                                         well_type=self.well_type)
             self.add_layout_pin_rect_center(text="D",

compiler/pgates/pwrite_driver.py

@@ -44,8 +44,6 @@ class pwrite_driver(design.design):
             self.create_layout()
             self.DRC_LVS()
 
-
-
     def create_netlist(self):
         self.add_pins()
         self.add_modules()
@@ -56,8 +54,6 @@ class pwrite_driver(design.design):
         self.route_wires()
         self.route_supplies()
         
-        
-        
     def add_pins(self):
         self.add_pin("din", "INPUT")
         self.add_pin("bl", "OUTPUT")
@@ -66,17 +62,19 @@ class pwrite_driver(design.design):
         self.add_pin("vdd", "POWER")
         self.add_pin("gnd", "GROUND")
 
-        
     def add_modules(self):
 
         # Tristate inverter
         self.tri = factory.create(module_type="ptristate_inv", height="min")
         self.add_mod(self.tri)
-        debug.check(self.tri.width<self.width,"Could not create tristate inverter to match bitcell width")
+        debug.check(self.tri.width<self.width,
+                    "Could not create tristate inverter to match bitcell width")
 
-        #self.tbuf = factory.create(module_type="ptristate_buf", height="min")
+        #self.tbuf = factory.create(module_type="ptristate_buf",
+        #height="min")
         #self.add_mod(self.tbuf)
-        #debug.check(self.tbuf.width<self.width,"Could not create tristate buffer to match bitcell width")
+        #debug.check(self.tbuf.width<self.width,
+        #"Could not create tristate buffer to match bitcell width")
         
         # Inverter for din and en
         self.inv = factory.create(module_type="pinv", under_rail_vias=True)

technology/freepdk45/tech/tech.py

@@ -12,6 +12,11 @@ from module_type import *
 """
 File containing the process technology parameters for FreePDK 45nm.
 """
+
+###################################################
+# Custom modules
+###################################################
+
 # This uses the default classes to instantiate module from
 # '$OPENRAM_HOME/compiler/modules'.
 # Using tech_modules['cellname'] you can override each class by providing a custom
@@ -19,7 +24,11 @@ File containing the process technology parameters for FreePDK 45nm.
 # For example: tech_modules['contact'] = 'contact_freepdk45'
 tech_modules = ModuleType()
 
-#GDS file info
+
+###################################################
+# GDS file info
+###################################################
+
 GDS = {}
 # gds units 
 # From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
@@ -136,7 +145,10 @@ drc["minlength_channel"] = 0.05
 drc["pwell_to_nwell"] = 0.225
 # WELL.3 Minimum spacing of nwell/pwell at the same potential
 # WELL.4 Minimum width of nwell/pwell
-drc.add_layer("well",
+drc.add_layer("nwell",
+              width = 0.2,
+              spacing = 0.135)
+drc.add_layer("pwell",
               width = 0.2,
               spacing = 0.135)
 
@@ -165,7 +177,10 @@ drc.add_layer("active",
               width = 0.09,
               spacing = 0.08)
 # ACTIVE.3 Minimum enclosure/spacing of nwell/pwell to active
-drc.add_enclosure("well",
+drc.add_enclosure("nwell",
+                  layer = "active",
+                  enclosure = 0.055)
+drc.add_enclosure("pwell",
                   layer = "active",
                   enclosure = 0.055)
 

technology/scn4m_subm/tech/tech.py

@@ -12,6 +12,11 @@ from module_type import *
 """
 File containing the process technology parameters for SCMOS 4m, 0.35um
 """
+
+###################################################
+# Custom modules
+###################################################
+
 # This uses the default classes to instantiate module from
 # '$OPENRAM_HOME/compiler/modules'.
 # Using tech_modules['cellname'] you can override each class by providing a custom
@@ -19,7 +24,10 @@ File containing the process technology parameters for SCMOS 4m, 0.35um
 # For example: tech_modules['contact'] = 'contact_scn4m'
 tech_modules = ModuleType()
 
-#GDS file info
+
+###################################################
+# GDS file info
+###################################################
 GDS={}
 # gds units
 # From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
@@ -69,8 +77,6 @@ preferred_directions = {"poly": "V",
 
 # create the GDS layer map
 layer={} 
-layer["vtg"]            = None
-layer["vth"]            = None
 layer["pwell"]          = (41, 0)
 layer["nwell"]          = (42, 0)
 layer["active"]         = (43, 0)
@@ -124,7 +130,10 @@ drc["minlength_channel"] = 2*_lambda_
 drc["pwell_to_nwell"] = 0
 # 1.3 Minimum spacing between wells of same type (if both are drawn)
 # 1.1 Minimum width
-drc.add_layer("well",
+drc.add_layer("nwell",
+              width = 12*_lambda_,
+              spacing = 6*_lambda_)
+drc.add_layer("pwell",
               width = 12*_lambda_,
               spacing = 6*_lambda_)
 
@@ -151,7 +160,10 @@ drc.add_layer("active",
               spacing = 4*_lambda_)
 
 # 2.3 Source/drain active to well edge 
-drc.add_enclosure("well",
+drc.add_enclosure("nwell",
+                  layer = "active",
+                  enclosure = 6*_lambda_)
+drc.add_enclosure("pwell",
                   layer = "active",
                   enclosure = 6*_lambda_)