luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Don't add sense amp to write only port. Fix write_and None define.

This commit is contained in:
Matt Guthaus 2019-08-11 08:46:36 -07:00
parent d56a972d61
commit e5618b88af
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
compiler/modules/port_data.py
View File

@ -157,10 +157,13 @@ class port_data(design.design):
bitcell_br=self.br_names[self.port]) bitcell_br=self.br_names[self.port])
self.add_mod(self.precharge_array) self.add_mod(self.precharge_array)
self.sense_amp_array = factory.create(module_type="sense_amp_array", if self.port in self.read_ports:
word_size=self.word_size, self.sense_amp_array = factory.create(module_type="sense_amp_array",
words_per_row=self.words_per_row) word_size=self.word_size,
self.add_mod(self.sense_amp_array) words_per_row=self.words_per_row)
self.add_mod(self.sense_amp_array)
else:
self.sense_amp_array = None
if self.col_addr_size > 0: if self.col_addr_size > 0:
@ -187,7 +190,7 @@ class port_data(design.design):
write_size=self.write_size) write_size=self.write_size)
self.add_mod(self.write_mask_and_array) self.add_mod(self.write_mask_and_array)
else: else:
self.write_mask_and_array_inst = None self.write_mask_and_array = None
else: else:
self.write_driver_array = None self.write_driver_array = None