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Merge branch 'singleport_refactor' of github.com:VLSIDA/PrivateRAM into singleport_refactor

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Jesse Cirimelli-Low
2023-08-14 18:53:22 -07:00
parent 0391bf6593 cd1b0f973d
commit e4c15d33c4
9 changed files with 166 additions and 333 deletions
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compiler/modules/column_decoder.py
+1 -1
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@@ -42,7 +42,7 @@ class column_decoder(design):
def create_instances(self):
self.column_decoder_inst = self.add_inst(name="column_decoder",
mod=self.column_decoder)
self.connect_inst(list(self.pins))
self.connect_inst(self.pins)
def create_layout(self):
self.column_decoder_inst.place(vector(0,0))
compiler/modules/pbitcell.py
+1 -1
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@@ -1212,7 +1212,7 @@ class pbitcell(bitcell_base):
if self.dummy_bitcell:
return
pin_dict = {pin: port for pin, port in zip(list(self.pins), port_nets)}
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
# Edges added wl->bl, wl->br for every port except write ports
rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names)