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OpenRAM
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Default drc and lvs errors is skipped.

This commit is contained in:
mrg 2020-07-13 14:08:00 -07:00
parent 716798baae
commit e49236f8fc
2 changed files with 14 additions and 32 deletions
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32
compiler/base/hierarchy_design.py
View File

@ -36,6 +36,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
else: else:
self.lvs_file = self.sp_file self.lvs_file = self.sp_file
self.drc_errors = "skipped"
self.lvs_errors = "skipped"
self.name = name self.name = name
hierarchy_spice.spice.__init__(self, name) hierarchy_spice.spice.__init__(self, name)
hierarchy_layout.layout.__init__(self, name) hierarchy_layout.layout.__init__(self, name)
@ -58,15 +61,12 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
# No layout to check # No layout to check
if OPTS.netlist_only: if OPTS.netlist_only:
self.drc_errors = "skipped" return
self.lvs_errors = "skipped"
# Unit tests will check themselves. # Unit tests will check themselves.
elif not force_check and OPTS.is_unit_test: elif not force_check and OPTS.is_unit_test:
self.drc_errors = "skipped" return
self.lvs_errors = "skipped"
elif not force_check and not OPTS.check_lvsdrc: elif not force_check and not OPTS.check_lvsdrc:
self.drc_errors = "skipped" return
self.lvs_errors = "skipped"
# Do not run if disabled in options. # Do not run if disabled in options.
elif (OPTS.inline_lvsdrc or force_check or final_verification): elif (OPTS.inline_lvsdrc or force_check or final_verification):
@ -92,12 +92,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
os.remove(tempspice) os.remove(tempspice)
os.remove(tempgds) os.remove(tempgds)
else:
self.drc_errors = "skipped"
self.lvs_errors = "skipped"
return (self.drc_errors, self.lvs_errors)
def DRC(self, final_verification=False): def DRC(self, final_verification=False):
"""Checks DRC for a module""" """Checks DRC for a module"""
import verify import verify
@ -107,7 +101,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
# No layout to check # No layout to check
if OPTS.netlist_only: if OPTS.netlist_only:
self.drc_errors = "skipped" return
elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name)
self.gds_write(tempgds) self.gds_write(tempgds)
@ -119,11 +113,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
if OPTS.purge_temp: if OPTS.purge_temp:
os.remove(tempgds) os.remove(tempgds)
else:
self.drc_errors = "skipped"
return self.drc_errors
def LVS(self, final_verification=False): def LVS(self, final_verification=False):
"""Checks LVS for a module""" """Checks LVS for a module"""
import verify import verify
@ -133,7 +122,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
# No layout to check # No layout to check
if OPTS.netlist_only: if OPTS.netlist_only:
self.lvs_errors = "skipped" return
elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name)
tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name)
@ -146,11 +135,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
if OPTS.purge_temp: if OPTS.purge_temp:
os.remove(tempspice) os.remove(tempspice)
os.remove(tempgds) os.remove(tempgds)
else:
self.lvs_errors = "skipped"
return self.lvs_errors
def init_graph_params(self): def init_graph_params(self):
"""Initializes parameters relevant to the graph creation""" """Initializes parameters relevant to the graph creation"""

14
compiler/pgates/ptx.py
View File

@ -12,7 +12,6 @@ from vector import vector
from sram_factory import factory from sram_factory import factory
import contact import contact
import logical_effort import logical_effort
import os
from globals import OPTS from globals import OPTS
from pgate import pgate from pgate import pgate
@ -120,11 +119,10 @@ class ptx(design.design):
def create_netlist(self): def create_netlist(self):
pin_list = ["D", "G", "S", "B"] pin_list = ["D", "G", "S", "B"]
if self.tx_type == "nmos": if self.tx_type == "nmos":
body_dir = 'GROUND' body_dir = "GROUND"
else: else:
# Assumed that the check for either pmos or nmos is done elsewhere. body_dir = "POWER"
body_dir = 'POWER' dir_list = ["INOUT", "INPUT", "INOUT", body_dir]
dir_list = ['INOUT', 'INPUT', 'INOUT', body_dir]
self.add_pin_list(pin_list, dir_list) self.add_pin_list(pin_list, dir_list)
# Just make a guess since these will actually # Just make a guess since these will actually
@ -135,9 +133,9 @@ class ptx(design.design):
# sky130 simulation cannot use the mult parameter in simulation # sky130 simulation cannot use the mult parameter in simulation
(self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width) (self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width)
main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type],
self.mults, self.mults,
self.tx_width, self.tx_width,
drc("minwidth_poly")) drc("minwidth_poly"))
# Perimeters are in microns # Perimeters are in microns
# Area is in u since it is microns square # Area is in u since it is microns square
area_str = "pd={0:.2f} ps={0:.2f} as={1:.2f}u ad={1:.2f}u".format(perimeter_sd, area_str = "pd={0:.2f} ps={0:.2f} as={1:.2f}u ad={1:.2f}u".format(perimeter_sd,