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Add per tool lvs directories

This commit is contained in:
mrg 2021-12-17 10:21:34 -08:00
parent 4fa084f272
commit e460eff014
1 changed files with 29 additions and 24 deletions
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21
compiler/base/hierarchy_spice.py
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@ -17,6 +17,7 @@ from wire_spice_model import wire_spice_model
from power_data import power_data from power_data import power_data
import logical_effort import logical_effort
class spice(): class spice():
""" """
This provides a set of useful generic types for hierarchy This provides a set of useful generic types for hierarchy
@ -36,14 +37,15 @@ class spice():
# If we have a separate lvs directory, then all the lvs files # If we have a separate lvs directory, then all the lvs files
# should be in there (all or nothing!) # should be in there (all or nothing!)
try: try:
lvs_subdir = tech.lvs_lib from tech import lvs_name
except AttributeError: lvs_dir = OPTS.openram_tech + lvs_name + "_lvs_lib/"
lvs_subdir = "lvs_lib" except ImportError:
lvs_dir = OPTS.openram_tech + lvs_subdir + "/" lvs_dir = OPTS.openram_tech + "lvs_lib/"
if not os.path.exists(lvs_dir):
lvs_dir = OPTS.openram_tech + "lvs_lib/"
if os.path.exists(lvs_dir): self.lvs_file = lvs_dir + cell_name + ".sp"
self.lvs_file = lvs_dir + cell_name + ".sp" if not os.path.exists(self.lvs_file):
else:
self.lvs_file = self.sp_file self.lvs_file = self.sp_file
self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "BIAS", "POWER", "GROUND"] self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "BIAS", "POWER", "GROUND"]
@ -277,7 +279,10 @@ class spice():
# parses line into ports and remove subckt # parses line into ports and remove subckt
lvs_pins = subckt_line.split(" ")[2:] lvs_pins = subckt_line.split(" ")[2:]
debug.check(lvs_pins == self.pins, debug.check(lvs_pins == self.pins,
"Spice netlists for LVS and simulation have port mismatches: {0} (LVS) vs {1} (sim)".format(lvs_pins, self.pins)) "Spice netlists for LVS and simulation have port mismatches:\n{0} (LVS {1})\nvs\n{2} (sim {3})".format(lvs_pins,
self.lvs_file,
self.pins,
self.sp_file))
def check_net_in_spice(self, net_name): def check_net_in_spice(self, net_name):
"""Checks if a net name exists in the current. Intended to be check nets in hand-made cells.""" """Checks if a net name exists in the current. Intended to be check nets in hand-made cells."""