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Added graph creation and functions in base class and lower level modules.

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This commit is contained in:
Hunter Nichols
2019-04-24 14:23:22 -07:00
parent 4f28295e20
commit e292767166
23 changed files with 196 additions and 10 deletions
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compiler/tests/05_bitcell_1rw_1r_array_test.py
+1 -1
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@@ -26,7 +26,7 @@ class bitcell_1rw_1r_array_test(openram_test):
OPTS.num_w_ports = 0
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/05_bitcell_array_test.py
+1 -1
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@@ -22,7 +22,7 @@ class array_test(openram_test):
debug.info(2, "Testing 4x4 array for 6t_cell")
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/12_tri_gate_array_test.py
+1 -1
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@@ -20,7 +20,7 @@ class tri_gate_array_test(openram_test):
debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
a = factory.create(module_type="tri_gate_array", columns=8, word_size=8)
self.local_check(a)
debug.info(1, "Testing tri_gate_array for columns=16, word_size=8")
a = factory.create(module_type="tri_gate_array", columns=16, word_size=8)
self.local_check(a)
compiler/tests/21_hspice_delay_test.py
+17
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@@ -33,6 +33,23 @@ class timing_sram_test(openram_test):
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c)
#Exclude things known not to be in critical path.
#Intended for characterizing read paths. Somewhat hacky implementation
s.s.bank.bitcell_array.graph_exclude_bits(15,0)
s.s.bank.graph_exclude_precharge()
s.s.graph_exclude_addr_dff()
s.s.graph_exclude_data_dff()
debug.info(1,'pins={}'.format(s.s.pins))
import graph_util
graph = graph_util.graph()
pins=['DIN0[0]', 'ADDR0[0]', 'ADDR0[1]', 'ADDR0[2]', 'ADDR0[3]', 'csb0', 'web0', 'clk0', 'DOUT0[0]', 'vdd', 'gnd']
s.s.build_graph(graph,"Xsram",pins)
graph.remove_edges('vdd')
graph.remove_edges('gnd')
debug.info(1,"{}".format(graph))
graph.printAllPaths('clk0', 'DOUT0[0]')
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)