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Added graph creation and functions in base class and lower level modules.
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@@ -50,3 +50,11 @@ class dff(design.design):
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#Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width.
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return parameter["dff_clk_cin"]
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges to graph. Handmade cells must implement this manually."""
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#The cell has 5 net ports hard-coded in self.pin_names. The edges
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#are based on the hard-coded name positions.
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# The edges added are: clk->Q.
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# Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
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graph.add_edge(port_nets[2],port_nets[1])
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