Added graph creation and functions in base class and lower level modules.

compiler/bitcells/bitcell.py

@@ -24,7 +24,7 @@ class bitcell(design.design):
         self.width = bitcell.width
         self.height = bitcell.height
         self.pin_map = bitcell.pin_map
-
+        
     def analytical_delay(self, corner, slew, load=0, swing = 0.5):
         parasitic_delay = 1
         size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
@@ -74,3 +74,12 @@ class bitcell(design.design):
         #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
         access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
         return 2*access_tx_cin
+
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges to graph. Handmade cells must implement this manually."""
+        #The bitcell has 5 net ports hard-coded in self.pin_names. The edges
+        #are based on the hard-coded name positions.
+        # The edges added are: wl->bl, wl->br.
+        # Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
+        graph.add_edge(port_nets[2],port_nets[0])
+        graph.add_edge(port_nets[2],port_nets[1])

compiler/bitcells/bitcell_1rw_1r.py

@@ -99,3 +99,15 @@ class bitcell_1rw_1r(design.design):
         #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
         access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
         return 2*access_tx_cin
+        
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges to graph. Handmade cells must implement this manually."""
+        #The bitcell has 8 net ports hard-coded in self.pin_names. The edges
+        #are based on the hard-coded name positions.
+        # The edges added are: wl0->bl0, wl0->br0, wl1->bl1, wl1->br1.
+        # Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
+        graph.add_edge(port_nets[4],port_nets[0])
+        graph.add_edge(port_nets[4],port_nets[1])    
+        graph.add_edge(port_nets[5],port_nets[2])
+        graph.add_edge(port_nets[5],port_nets[3]) 
+        

compiler/bitcells/bitcell_1w_1r.py

@@ -99,3 +99,14 @@ class bitcell_1w_1r(design.design):
         #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
         access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
         return 2*access_tx_cin
+        
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges to graph. Handmade cells must implement this manually."""
+        #The bitcell has 8 net ports hard-coded in self.pin_names. The edges
+        #are based on the hard-coded name positions.
+        # The edges added are: wl0->bl0, wl0->br0, wl1->bl1, wl1->br1.
+        # Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
+        graph.add_edge(port_nets[4],port_nets[0])
+        graph.add_edge(port_nets[4],port_nets[1])    
+        graph.add_edge(port_nets[5],port_nets[2])
+        graph.add_edge(port_nets[5],port_nets[3])     

compiler/bitcells/pbitcell.py

@@ -893,3 +893,15 @@ class pbitcell(design.design):
         access_tx_cin = self.readwrite_nmos.get_cin()
         return 2*access_tx_cin
 
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges to graph. Done manually to make the graph acyclic."""
+        #The base graph function can make this but it would contain loops and path
+        #searches would essentially be useless.
+        # Edges added wl->bl, wl->br for every port
+        
+        num_wl = len(self.rw_wl_names) + len(self.w_wl_names) + len(self.r_wl_names)
+        wl_pos = 2*num_wl #there are this many bitlines nets before the wls in the port list
+        for i in range(num_wl):
+            bl_pos = i*2
+            graph.add_edge(port_nets[wl_pos+i],port_nets[bl_pos])
+            graph.add_edge(port_nets[wl_pos+i],port_nets[bl_pos+1])

compiler/bitcells/replica_bitcell.py

@@ -29,3 +29,12 @@ class replica_bitcell(design.design):
         #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
         access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
         return 2*access_tx_cin
+
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges to graph. Handmade cells must implement this manually."""
+        #The bitcell has 5 net ports hard-coded in self.pin_names. The edges
+        #are based on the hard-coded name positions.
+        # The edges added are: wl->bl, wl->br.
+        # Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
+        graph.add_edge(port_nets[2],port_nets[0])
+        graph.add_edge(port_nets[2],port_nets[1])

compiler/bitcells/replica_bitcell_1rw_1r.py

@@ -30,3 +30,14 @@ class replica_bitcell_1rw_1r(design.design):
         #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
         access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
         return 2*access_tx_cin
+
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges to graph. Handmade cells must implement this manually."""
+        #The bitcell has 8 net ports hard-coded in self.pin_names. The edges
+        #are based on the hard-coded name positions.
+        # The edges added are: wl0->bl0, wl0->br0, wl1->bl1, wl1->br1.
+        # Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
+        graph.add_edge(port_nets[4],port_nets[0])
+        graph.add_edge(port_nets[4],port_nets[1])    
+        graph.add_edge(port_nets[5],port_nets[2])
+        graph.add_edge(port_nets[5],port_nets[3]) 

compiler/bitcells/replica_bitcell_1w_1r.py

@@ -30,3 +30,14 @@ class replica_bitcell_1w_1r(design.design):
         #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
         access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
         return 2*access_tx_cin
+
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges to graph. Handmade cells must implement this manually."""
+        #The bitcell has 8 net ports hard-coded in self.pin_names. The edges
+        #are based on the hard-coded name positions.
+        # The edges added are: wl0->bl0, wl0->br0, wl1->bl1, wl1->br1.
+        # Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
+        graph.add_edge(port_nets[4],port_nets[0])
+        graph.add_edge(port_nets[4],port_nets[1])    
+        graph.add_edge(port_nets[5],port_nets[2])
+        graph.add_edge(port_nets[5],port_nets[3])