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merge in dev

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This commit is contained in:
Jesse Cirimelli-Low
2023-08-10 17:04:45 -07:00
parent be72bcfa01 cc8161afc1
commit e23289d5ae
81 changed files with 11306 additions and 4530 deletions
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compiler/modules/column_decoder.py
+1 -1
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@@ -42,7 +42,7 @@ class column_decoder(design):
def create_instances(self):
self.column_decoder_inst = self.add_inst(name="column_decoder",
mod=self.column_decoder)
self.connect_inst(self.pins)
self.connect_inst(list(self.pins))
def create_layout(self):
self.column_decoder_inst.place(vector(0,0))
compiler/modules/pbitcell.py
+1 -1
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@@ -1212,7 +1212,7 @@ class pbitcell(bitcell_base):
if self.dummy_bitcell:
return
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
pin_dict = {pin: port for pin, port in zip(list(self.pins), port_nets)}
# Edges added wl->bl, wl->br for every port except write ports
rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names)
compiler/modules/rom_bank.py
+16 -29
View File
@@ -14,7 +14,6 @@ from openram.base import rom_verilog
from openram import OPTS, print_time
from openram.sram_factory import factory
from openram.tech import drc, layer, parameter
from openram.router import router_tech
class rom_bank(design,rom_verilog):
@@ -111,21 +110,16 @@ class rom_bank(design,rom_verilog):
self.place_top_level_pins()
self.route_output_buffers()
rt = router_tech(self.supply_stack, 1)
init_bbox = self.get_bbox(side="ring",
margin=rt.track_width)
self.route_supplies(init_bbox)
# We need the initial bbox for the supply rings later
# because the perimeter pins will change the bbox
# FIXME: Somehow ROM layout behaves weird and doesn't add all the pin
# shapes before routing supplies
init_bbox = self.get_bbox()
if OPTS.route_supplies:
self.route_supplies(init_bbox)
# Route the pins to the perimeter
if OPTS.perimeter_pins:
# We now route the escape routes far enough out so that they will
# reach past the power ring or stripes on the sides
bbox = self.get_bbox(side="ring",
margin=11*rt.track_width)
self.route_escape_pins(bbox)
self.route_escape_pins(init_bbox)
def setup_layout_constants(self):
@@ -450,24 +444,17 @@ class rom_bank(design,rom_verilog):
pin_num = msb - self.col_bits
self.add_io_pin(self.decode_inst, "A{}".format(pin_num), name)
def route_supplies(self, bbox=None):
def route_supplies(self, bbox):
for pin_name in ["vdd", "gnd"]:
for inst in self.insts:
self.copy_power_pins(inst, pin_name)
if not OPTS.route_supplies:
# Do not route the power supply (leave as must-connect pins)
return
elif OPTS.route_supplies == "grid":
from openram.router import supply_grid_router as router
else:
from openram.router import supply_tree_router as router
rtr=router(layers=self.supply_stack,
design=self,
bbox=bbox,
pin_type=OPTS.supply_pin_type)
from openram.router import supply_router as router
rtr = router(layers=self.supply_stack,
design=self,
bbox=bbox,
pin_type=OPTS.supply_pin_type)
rtr.route()
if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]:
@@ -507,7 +494,7 @@ class rom_bank(design,rom_verilog):
pins_to_route.append("clk")
pins_to_route.append("cs")
from openram.router import signal_escape_router as router
rtr=router(layers=self.m3_stack,
design=self,
bbox=bbox)
rtr.escape_route(pins_to_route)
rtr = router(layers=self.m3_stack,
bbox=bbox,
design=self)
rtr.route(pins_to_route)
compiler/modules/sram_1bank.py
+15 -32
View File
@@ -14,7 +14,6 @@ from openram.base import channel_route
from openram.base import design
from openram.base import verilog
from openram.base import lef
from openram.router import router_tech
from openram.sram_factory import factory
from openram.tech import spice
from openram import OPTS, print_time
@@ -252,18 +251,11 @@ class sram_1bank(design, verilog, lef):
for inst in self.insts:
self.copy_power_pins(inst, pin_name, self.ext_supply[pin_name])
if not OPTS.route_supplies:
# Do not route the power supply (leave as must-connect pins)
return
elif OPTS.route_supplies == "grid":
from openram.router import supply_grid_router as router
else:
from openram.router import supply_tree_router as router
rtr=router(layers=self.supply_stack,
design=self,
bbox=bbox,
pin_type=OPTS.supply_pin_type)
from openram.router import supply_router as router
rtr = router(layers=self.supply_stack,
design=self,
bbox=bbox,
pin_type=OPTS.supply_pin_type)
rtr.route()
if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]:
@@ -288,7 +280,7 @@ class sram_1bank(design, verilog, lef):
pin.width(),
pin.height())
elif OPTS.route_supplies and OPTS.supply_pin_type == "single":
elif OPTS.supply_pin_type == "single":
# Update these as we may have routed outside the region (perimeter pins)
lowest_coord = self.find_lowest_coords()
@@ -326,7 +318,7 @@ class sram_1bank(design, verilog, lef):
# Grid is left with many top level pins
pass
def route_escape_pins(self, bbox):
def route_escape_pins(self, bbox=None):
"""
Add the top-level pins for a single bank SRAM with control.
"""
@@ -370,10 +362,10 @@ class sram_1bank(design, verilog, lef):
pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
from openram.router import signal_escape_router as router
rtr=router(layers=self.m3_stack,
design=self,
bbox=bbox)
rtr.escape_route(pins_to_route)
rtr = router(layers=self.m3_stack,
bbox=bbox,
design=self)
rtr.route(pins_to_route)
def compute_bus_sizes(self):
""" Compute the independent bus widths shared between two and four bank SRAMs """
@@ -1077,24 +1069,15 @@ class sram_1bank(design, verilog, lef):
# Some technologies have an isolation
self.add_dnwell(inflate=2.5)
init_bbox = self.get_bbox()
# Route the supplies together and/or to the ring/stripes.
# This is done with the original bbox since the escape routes need to
# be outside of the ring for OpenLane
rt = router_tech(self.supply_stack, 1)
init_bbox = self.get_bbox(side="ring",
margin=rt.track_width)
# We need the initial bbox for the supply rings later
# because the perimeter pins will change the bbox
# Route the pins to the perimeter
if OPTS.perimeter_pins:
# We now route the escape routes far enough out so that they will
# reach past the power ring or stripes on the sides
bbox = self.get_bbox(side="ring",
margin=11*rt.track_width)
self.route_escape_pins(bbox)
self.route_supplies(init_bbox)
self.route_escape_pins(init_bbox)
if OPTS.route_supplies:
self.route_supplies(init_bbox)
def route_dffs(self, add_routes=True):