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Converted all submodules to use _bit notation instead of [bit]

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This commit is contained in:
Matt Guthaus
2018-10-11 09:53:08 -07:00
parent 6ef1a3c755
commit e22e658090
23 changed files with 330 additions and 330 deletions
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compiler/modules/bitcell_array.py
+4 -4
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@@ -69,10 +69,10 @@ class bitcell_array(design.design):
column_list = self.cell.list_all_bitline_names()
for col in range(self.column_size):
for cell_column in column_list:
self.add_pin(cell_column+"[{0}]".format(col))
self.add_pin(cell_column+"_{0}".format(col))
for row in range(self.row_size):
for cell_row in row_list:
self.add_pin(cell_row+"[{0}]".format(row))
self.add_pin(cell_row+"_{0}".format(row))
self.add_pin("vdd")
self.add_pin("gnd")
@@ -105,7 +105,7 @@ class bitcell_array(design.design):
for col in range(self.column_size):
for cell_column in column_list:
bl_pin = self.cell_inst[0,col].get_pin(cell_column)
self.add_layout_pin(text=cell_column+"[{0}]".format(col),
self.add_layout_pin(text=cell_column+"_{0}".format(col),
layer="metal2",
offset=bl_pin.ll(),
width=bl_pin.width(),
@@ -118,7 +118,7 @@ class bitcell_array(design.design):
for row in range(self.row_size):
for cell_row in row_list:
wl_pin = self.cell_inst[row,0].get_pin(cell_row)
self.add_layout_pin(text=cell_row+"[{0}]".format(row),
self.add_layout_pin(text=cell_row+"_{0}".format(row),
layer="metal1",
offset=wl_pin.ll(),
width=self.width,