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simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations

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Michael Timothy Grimes
2018-05-31 17:39:51 -07:00
parent 9e739d67d4
commit e19a422696
3 changed files with 211 additions and 108 deletions
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compiler/tests/05_pbitcell_array_test.py
+11 -2
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@@ -28,12 +28,21 @@ class array_multiport_test(openram_test):
OPTS.r_ports = 2
OPTS.w_ports = 2
debug.info(2, "Testing 4x4 array for multiport bitcell")
debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
OPTS.rw_ports = 2
OPTS.r_ports = 0
OPTS.w_ports = 2
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
OPTS.check_lvsdrc = True
#globals.end_openram()
globals.end_openram()
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":