simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations

2026-08-30 01:48:33 +02:00 · 2018-05-31 17:39:51 -07:00
parent 9e739d67d4
commit e19a422696
3 changed files with 211 additions and 108 deletions
@@ -21,7 +21,7 @@ class bitcell_array(design.design):
        self.column_size = cols
        self.row_size = rows

-        #from importlib import reload
+        from importlib import reload
        c = reload(__import__(OPTS.bitcell))
        self.mod_bitcell = getattr(c, OPTS.bitcell)
        self.cell = self.mod_bitcell()