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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 11:08:01 +02:00
Clean up new code for add_modules, add_pins and netlist/layouts.
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@@ -20,9 +20,9 @@ class precharge_array(design.design):
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debug.info(1, "Creating {0}".format(self.name))
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self.columns = columns
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self.pc_cell = precharge(name="precharge", size=size, bitcell_bl=bitcell_bl, bitcell_br=bitcell_br)
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self.add_mod(self.pc_cell)
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self.size = size
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self.bitcell_bl = bitcell_bl
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self.bitcell_br = bitcell_br
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self.create_netlist()
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if not OPTS.netlist_only:
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@@ -37,6 +37,7 @@ class precharge_array(design.design):
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self.add_pin("vdd")
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_insts()
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@@ -47,8 +48,15 @@ class precharge_array(design.design):
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self.place_insts()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_modules(self):
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self.pc_cell = precharge(name="precharge",
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size=self.size,
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bitcell_bl=self.bitcell_bl,
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bitcell_br=self.bitcell_br)
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self.add_mod(self.pc_cell)
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def add_layout_pins(self):
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self.add_layout_pin(text="en",
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