Clean up new code for add_modules, add_pins and netlist/layouts.

compiler/modules/bank.py

@@ -22,17 +22,6 @@ class bank(design.design):
 
     def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""):
 
-        mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver",
-                    "bitcell_array",   "sense_amp_array",    "precharge_array",
-                    "column_mux_array", "write_driver_array", 
-                    "dff", "bank_select"]
-        from importlib import reload
-        for mod_name in mod_list:
-            config_mod_name = getattr(OPTS, mod_name)
-            class_file = reload(__import__(config_mod_name))
-            mod_class = getattr(class_file , config_mod_name)
-            setattr (self, "mod_"+mod_name, mod_class)
-
         if name == "":
             name = "bank_{0}_{1}".format(word_size, num_words)
         design.design.__init__(self, name)
@@ -206,6 +195,19 @@ class bank(design.design):
 
     def add_modules(self):
         """ Create all the modules using the class loader """
+        
+        mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver",
+                    "bitcell_array",   "sense_amp_array",    "precharge_array",
+                    "column_mux_array", "write_driver_array", 
+                    "dff", "bank_select"]
+        from importlib import reload
+        for mod_name in mod_list:
+            config_mod_name = getattr(OPTS, mod_name)
+            class_file = reload(__import__(config_mod_name))
+            mod_class = getattr(class_file , config_mod_name)
+            setattr (self, "mod_"+mod_name, mod_class)
+
+        
         self.bitcell = self.mod_bitcell()
         
         self.bitcell_array = self.mod_bitcell_array(cols=self.num_cols,

compiler/modules/bitcell_array.py

@@ -21,16 +21,6 @@ class bitcell_array(design.design):
         self.column_size = cols
         self.row_size = rows
 
-        from importlib import reload
-        c = reload(__import__(OPTS.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.bitcell)
-        self.cell = self.mod_bitcell()
-        self.add_mod(self.cell)
-
-        # We increase it by a well enclosure so the precharges don't overlap our wells
-        self.height = self.row_size*self.cell.height + drc["well_enclosure_active"] + self.m1_width
-        self.width = self.column_size*self.cell.width + self.m1_width
-        
         self.create_netlist()
         if not OPTS.netlist_only:
             self.create_layout()
@@ -42,17 +32,16 @@ class bitcell_array(design.design):
         
     def create_netlist(self):
         """ Create and connect the netlist """
+        self.add_modules()
         self.add_pins()
-        
-        self.cell_inst = {}
-        for col in range(self.column_size):
-            for row in range(self.row_size):
-                name = "bit_r{0}_c{1}".format(row, col)
-                self.cell_inst[row,col]=self.add_inst(name=name,
-                                                      mod=self.cell)
-                self.connect_inst(self.cell.list_bitcell_pins(col, row))
+        self.create_modules()
 
     def create_layout(self):
+
+        # We increase it by a well enclosure so the precharges don't overlap our wells
+        self.height = self.row_size*self.cell.height + drc["well_enclosure_active"] + self.m1_width
+        self.width = self.column_size*self.cell.width + self.m1_width
+        
         xoffset = 0.0
         for col in range(self.column_size):
             yoffset = 0.0
@@ -87,7 +76,25 @@ class bitcell_array(design.design):
         self.add_pin("vdd")
         self.add_pin("gnd")
 
-            
+    def add_modules(self):
+        """ Add the modules used in this design """
+
+        from importlib import reload
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
+        self.cell = self.mod_bitcell()
+        self.add_mod(self.cell)
+
+    def create_modules(self):
+        """ Create the module instances used in this design """
+        self.cell_inst = {}
+        for col in range(self.column_size):
+            for row in range(self.row_size):
+                name = "bit_r{0}_c{1}".format(row, col)
+                self.cell_inst[row,col]=self.add_inst(name=name,
+                                                      mod=self.cell)
+                self.connect_inst(self.cell.list_bitcell_pins(col, row))
+        
     def add_layout_pins(self):
         """ Add the layout pins """
         

compiler/modules/delay_chain.py

@@ -30,8 +30,8 @@ class delay_chain(design.design):
                 
 
     def create_netlist(self):
-        self.add_pins()
         self.add_modules()
+        self.add_pins()
         self.create_inverters()
         
     def create_layout(self):

compiler/modules/dff_array.py

@@ -20,27 +20,30 @@ class dff_array(design.design):
         design.design.__init__(self, name)
         debug.info(1, "Creating {0} rows={1} cols={2}".format(self.name, self.rows, self.columns))
 
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+    def create_netlist(self):
+        self.add_modules()
+        self.add_pins()
+        self.create_dff_array()
+        
+    def create_layout(self):
+        self.width = self.columns * self.dff.width
+        self.height = self.rows * self.dff.height
+        
+        self.place_dff_array()
+        self.add_layout_pins()
+        self.DRC_LVS()
+
+    def add_modules(self):
         from importlib import reload
         c = reload(__import__(OPTS.dff))
         self.mod_dff = getattr(c, OPTS.dff)
         self.dff = self.mod_dff("dff")
         self.add_mod(self.dff)
-
-        self.width = self.columns * self.dff.width
-        self.height = self.rows * self.dff.height
-
-        self.create_netlist()
-        self.create_layout()
-
-    def create_netlist(self):
-        self.add_pins()
-        self.create_dff_array()
         
-    def create_layout(self):
-        self.place_dff_array()
-        self.add_layout_pins()
-        self.DRC_LVS()
-
     def add_pins(self):
         for row in range(self.rows):  
             for col in range(self.columns):

compiler/modules/dff_buf.py

@@ -26,29 +26,41 @@ class dff_buf(design.design):
         debug.check(inv1_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
         debug.check(inv2_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")        
 
+        self.inv1_size=inv1_size
+        self.inv2_size=inv2_size
+        
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+    def create_netlist(self):
+        self.add_modules()
+        self.add_pins()
+        self.create_modules()
+
+    def create_layout(self):
+        self.width = self.dff.width + self.inv1.width + self.inv2.width
+        self.height = self.dff.height
+        
+        self.place_modules()
+        self.route_wires()
+        self.add_layout_pins()
+        self.DRC_LVS()
+
+    def add_modules(self):
         from importlib import reload
         c = reload(__import__(OPTS.dff))
         self.mod_dff = getattr(c, OPTS.dff)
         self.dff = self.mod_dff("dff")
         self.add_mod(self.dff)
 
-        self.inv1 = pinv(size=inv1_size,height=self.dff.height)
+        self.inv1 = pinv(size=self.inv1_size,height=self.dff.height)
         self.add_mod(self.inv1)
 
-        self.inv2 = pinv(size=inv2_size,height=self.dff.height)
+        self.inv2 = pinv(size=self.inv2_size,height=self.dff.height)
         self.add_mod(self.inv2)
 
-        self.width = self.dff.width + self.inv1.width + self.inv2.width
-        self.height = self.dff.height
-
-        self.create_layout()
-
-    def create_layout(self):
-        self.add_pins()
-        self.add_insts()
-        self.add_wires()
-        self.add_layout_pins()
-        self.DRC_LVS()
+        
         
     def add_pins(self):
         self.add_pin("D")
@@ -58,26 +70,30 @@ class dff_buf(design.design):
         self.add_pin("vdd")
         self.add_pin("gnd")
 
-    def add_insts(self):
-        # Add the DFF
+    def create_modules(self):
         self.dff_inst=self.add_inst(name="dff_buf_dff",
-                                    mod=self.dff,
-                                    offset=vector(0,0))
+                                    mod=self.dff)
         self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
 
-        # Add INV1 to the right
         self.inv1_inst=self.add_inst(name="dff_buf_inv1",
-                                     mod=self.inv1,
-                                     offset=vector(self.dff_inst.rx(),0))
+                                     mod=self.inv1)
         self.connect_inst(["qint", "Qb",  "vdd", "gnd"])
         
-        # Add INV2 to the right
         self.inv2_inst=self.add_inst(name="dff_buf_inv2",
-                                     mod=self.inv2,
-                                     offset=vector(self.inv1_inst.rx(),0))
+                                     mod=self.inv2)
         self.connect_inst(["Qb", "Q",  "vdd", "gnd"])
+
+    def place_modules(self):
+        # Add the DFF
+        self.dff_inst.place(vector(0,0))
+
+        # Add INV1 to the right
+        self.inv1_inst.place(vector(self.dff_inst.rx(),0))
         
-    def add_wires(self):
+        # Add INV2 to the right
+        self.inv2_inst.place(vector(self.inv1_inst.rx(),0))
+        
+    def route_wires(self):
         # Route dff q to inv1 a
         q_pin = self.dff_inst.get_pin("Q")
         a1_pin = self.inv1_inst.get_pin("A")

compiler/modules/dff_buf_array.py

@@ -29,7 +29,7 @@ class dff_buf_array(design.design):
 
     def create_netlist(self):
         self.add_pins()
-        self.add_dff()
+        self.add_modules()
         self.create_dff_array()
 
     def create_layout(self):
@@ -51,7 +51,7 @@ class dff_buf_array(design.design):
         self.add_pin("vdd")
         self.add_pin("gnd")
 
-    def add_dff(self):
+    def add_modules(self):
         self.dff = dff_buf.dff_buf(self.inv1_size, self.inv2_size)
         self.add_mod(self.dff)
 

compiler/modules/dff_inv.py

@@ -63,12 +63,10 @@ class dff_inv(design.design):
         self.add_mod(self.inv1)
 
     def create_modules(self):
-        # Add the DFF
         self.dff_inst=self.add_inst(name="dff_inv_dff",
                                     mod=self.dff)
         self.connect_inst(["D", "Q", "clk", "vdd", "gnd"])
 
-        # Add INV1 to the right
         self.inv1_inst=self.add_inst(name="dff_inv_inv1",
                                      mod=self.inv1)
         self.connect_inst(["Q", "Qb",  "vdd", "gnd"])

compiler/modules/dff_inv_array.py

@@ -28,7 +28,7 @@ class dff_inv_array(design.design):
 
     def create_netlist(self):
         self.add_pins()
-        self.add_dff()
+        self.add_modules()
         self.create_dff_array()
         
     def create_layout(self):
@@ -39,7 +39,7 @@ class dff_inv_array(design.design):
         self.add_layout_pins()
         self.DRC_LVS()
 
-    def add_dff(self):
+    def add_modules(self):
         self.dff = dff_inv.dff_inv(self.inv_size)
         self.add_mod(self.dff)
 

compiler/modules/ms_flop_array.py

@@ -20,27 +20,31 @@ class ms_flop_array(design.design):
         design.design.__init__(self, name)
         debug.info(1, "Creating {}".format(self.name))
 
+        self.words_per_row = int(self.columns / self.word_size)
+
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+    def create_netlist(self):
+        self.add_modules()
+        self.add_pins()
+        self.create_ms_flop_array()
+
+    def create_layout(self):
+        self.width = self.columns * self.ms.width
+        self.height = self.ms.height
+
+        self.place_ms_flop_array()
+        self.add_layout_pins()
+        self.DRC_LVS()
+
+    def add_modules(self):
         from importlib import reload
         c = reload(__import__(OPTS.ms_flop))
         self.mod_ms_flop = getattr(c, OPTS.ms_flop)
         self.ms = self.mod_ms_flop("ms_flop")
         self.add_mod(self.ms)
-
-        self.width = self.columns * self.ms.width
-        self.height = self.ms.height
-        self.words_per_row = int(self.columns / self.word_size)
-
-        self.create_netlist()
-        self.create_layout()
-
-    def create_netlist(self):
-        self.add_pins()
-        self.create_ms_flop_array()
-
-    def create_layout(self):
-        self.place_ms_flop_array()
-        self.add_layout_pins()
-        self.DRC_LVS()
         
     def add_pins(self):
         for i in range(self.word_size):

compiler/modules/precharge_array.py

@@ -20,9 +20,9 @@ class precharge_array(design.design):
         debug.info(1, "Creating {0}".format(self.name))
 
         self.columns = columns
-
-        self.pc_cell = precharge(name="precharge", size=size, bitcell_bl=bitcell_bl, bitcell_br=bitcell_br)
-        self.add_mod(self.pc_cell)
+        self.size = size
+        self.bitcell_bl = bitcell_bl
+        self.bitcell_br = bitcell_br
 
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -37,6 +37,7 @@ class precharge_array(design.design):
         self.add_pin("vdd")
 
     def create_netlist(self):
+        self.add_modules()
         self.add_pins()
         self.create_insts()
         
@@ -47,8 +48,15 @@ class precharge_array(design.design):
         self.place_insts()
         self.add_layout_pins()
         self.DRC_LVS()
-        
 
+    def add_modules(self):
+        self.pc_cell = precharge(name="precharge",
+                                 size=self.size,
+                                 bitcell_bl=self.bitcell_bl,
+                                 bitcell_br=self.bitcell_br)
+        self.add_mod(self.pc_cell)
+
+        
     def add_layout_pins(self):
 
         self.add_layout_pin(text="en",

compiler/modules/replica_bitline.py

@@ -18,13 +18,6 @@ class replica_bitline(design.design):
     def __init__(self, delay_stages, delay_fanout, bitcell_loads, name="replica_bitline"):
         design.design.__init__(self, name)
 
-        from importlib import reload
-        g = reload(__import__(OPTS.delay_chain))
-        self.mod_delay_chain = getattr(g, OPTS.delay_chain)
-
-        g = reload(__import__(OPTS.replica_bitcell))
-        self.mod_replica_bitcell = getattr(g, OPTS.replica_bitcell)
-        
         self.bitcell_loads = bitcell_loads
         self.delay_stages = delay_stages
         self.delay_fanout = delay_fanout
@@ -34,19 +27,17 @@ class replica_bitline(design.design):
             self.create_layout()
             
     def create_netlist(self):
-        for pin in ["en", "out", "vdd", "gnd"]:
-            self.add_pin(pin)
         self.add_modules()
+        self.add_pins()
         self.create_modules()
 
     def create_layout(self):
         self.calculate_module_offsets()
         self.place_modules()
         self.route()
+        self.add_layout_pins()
 
         self.offset_all_coordinates()
-        
-        self.add_layout_pins()
 
         #self.add_lvs_correspondence_points()
 
@@ -56,6 +47,9 @@ class replica_bitline(design.design):
 
         self.DRC_LVS()
 
+    def add_pins(self):
+        for pin in ["en", "out", "vdd", "gnd"]:
+            self.add_pin(pin)
 
     def calculate_module_offsets(self):
         """ Calculate all the module offsets """
@@ -85,6 +79,14 @@ class replica_bitline(design.design):
 
     def add_modules(self):
         """ Add the modules for later usage """
+
+        from importlib import reload
+        g = reload(__import__(OPTS.delay_chain))
+        self.mod_delay_chain = getattr(g, OPTS.delay_chain)
+
+        g = reload(__import__(OPTS.replica_bitcell))
+        self.mod_replica_bitcell = getattr(g, OPTS.replica_bitcell)
+        
         self.bitcell = self.replica_bitcell = self.mod_replica_bitcell()
         self.add_mod(self.bitcell)
 
@@ -267,8 +269,6 @@ class replica_bitline(design.design):
         self.copy_layout_pin(self.dc_inst,"vdd")
         self.copy_layout_pin(self.rbc_inst,"vdd")        
         
-
-        
         # Connect the WL and vdd pins directly to the center and right vdd rails
         # Connect RBL vdd pins to center and right rails
         rbl_vdd_pins = self.rbl_inst.get_pins("vdd")
@@ -288,9 +288,6 @@ class replica_bitline(design.design):
                                 offset=end,
                                 rotate=90)
 
-
-
-        
         # Add via for the inverter
         pin = self.rbl_inv_inst.get_pin("vdd")
         start = vector(self.left_vdd_pin.cx(),pin.cy())

compiler/modules/sense_amp_array.py

@@ -14,44 +14,46 @@ class sense_amp_array(design.design):
         design.design.__init__(self, "sense_amp_array")
         debug.info(1, "Creating {0}".format(self.name))
 
+        self.word_size = word_size
+        self.words_per_row = words_per_row
+        self.row_size = self.word_size * self.words_per_row
+
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+
+    def create_netlist(self):
+        self.add_modules()
+        self.add_pins()
+        self.create_sense_amp_array()
+
+    def create_layout(self):
+        self.height = self.amp.height
+        self.width = self.amp.width * self.word_size * self.words_per_row
+
+        self.place_sense_amp_array()
+        self.add_layout_pins()
+        self.route_rails()
+        self.DRC_LVS()
+
+    def add_pins(self):
+        for i in range(0,self.word_size):
+            self.add_pin("data[{0}]".format(i))
+            self.add_pin("bl[{0}]".format(i))
+            self.add_pin("br[{0}]".format(i))
+        self.add_pin("en")
+        self.add_pin("vdd")
+        self.add_pin("gnd")
+        
+    def add_modules(self):
         from importlib import reload
         c = reload(__import__(OPTS.sense_amp))
         self.mod_sense_amp = getattr(c, OPTS.sense_amp)
         self.amp = self.mod_sense_amp("sense_amp")
         self.add_mod(self.amp)
 
-        self.word_size = word_size
-        self.words_per_row = words_per_row
-        self.row_size = self.word_size * self.words_per_row
-
-        self.height = self.amp.height
-        self.width = self.amp.width * self.word_size * self.words_per_row
-
-        self.create_netlist()
-        self.create_layout()
-        self.DRC_LVS()
-
-    def add_pins(self):
-
-        for i in range(0,self.word_size):
-            self.add_pin("data[{0}]".format(i))
-            self.add_pin("bl[{0}]".format(i))
-            self.add_pin("br[{0}]".format(i))
-
-        self.add_pin("en")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
-
-    def create_netlist(self):
-        self.add_pins()
-        self.create_sense_amp_array()
         
-    def create_layout(self):
-        self.place_sense_amp_array()
-        self.add_layout_pins()
-        self.route_rails()
-        
-
     def create_sense_amp_array(self):
         self.local_insts = []
         for i in range(0,self.word_size):

compiler/modules/single_level_column_mux_array.py

@@ -6,7 +6,7 @@ from tech import drc
 import debug
 import math
 from vector import vector
-
+from globals import OPTS
 
 class single_level_column_mux_array(design.design):
     """
@@ -20,23 +20,14 @@ class single_level_column_mux_array(design.design):
         self.columns = columns
         self.word_size = word_size
         self.words_per_row = int(self.columns / self.word_size)
+        
         self.create_netlist()
-        self.create_layout()
-
-    def add_pins(self):
-        for i in range(self.columns):
-            self.add_pin("bl[{}]".format(i))
-            self.add_pin("br[{}]".format(i))
-        for i in range(self.words_per_row):
-            self.add_pin("sel[{}]".format(i))
-        for i in range(self.word_size):
-            self.add_pin("bl_out[{}]".format(i))
-            self.add_pin("br_out[{}]".format(i))
-        self.add_pin("gnd")
+        if not OPTS.netlist_only:
+            self.create_layout()
 
     def create_netlist(self):
-        self.add_pins()
         self.add_modules()
+        self.add_pins()
         self.create_array()
         
     def create_layout(self):
@@ -51,6 +42,17 @@ class single_level_column_mux_array(design.design):
 
         self.DRC_LVS()
         
+    def add_pins(self):
+        for i in range(self.columns):
+            self.add_pin("bl[{}]".format(i))
+            self.add_pin("br[{}]".format(i))
+        for i in range(self.words_per_row):
+            self.add_pin("sel[{}]".format(i))
+        for i in range(self.word_size):
+            self.add_pin("bl_out[{}]".format(i))
+            self.add_pin("br_out[{}]".format(i))
+        self.add_pin("gnd")
+
 
     def add_modules(self):
         # FIXME: Why is this 8x?

compiler/modules/tri_gate_array.py

@@ -14,31 +14,34 @@ class tri_gate_array(design.design):
         design.design.__init__(self, "tri_gate_array")
         debug.info(1, "Creating {0}".format(self.name))
 
+        self.columns = columns
+        self.word_size = word_size
+        self.words_per_row = int(self.columns / self.word_size)
+        
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+    def create_netlist(self):
+        self.add_modules()
+        self.add_pins()
+        self.create_array()
+        
+    def create_layout(self):
+        self.width = (self.columns / self.words_per_row) * self.tri.width
+        self.height = self.tri.height
+
+        self.place_array()
+        self.add_layout_pins()
+        self.DRC_LVS()
+
+    def add_modules(self):
         from importlib import reload
         c = reload(__import__(OPTS.tri_gate))
         self.mod_tri_gate = getattr(c, OPTS.tri_gate)
         self.tri = self.mod_tri_gate("tri_gate")
         self.add_mod(self.tri)
-
-        self.columns = columns
-        self.word_size = word_size
-
-        self.words_per_row = int(self.columns / self.word_size)
-        self.width = (self.columns / self.words_per_row) * self.tri.width
-        self.height = self.tri.height
         
-        self.create_netlist()
-        self.create_layout()
-
-    def create_netlist(self):
-        self.add_pins()
-        self.create_array()
-        
-    def create_layout(self):
-        self.place_array()
-        self.add_layout_pins()
-        self.DRC_LVS()
-
     def add_pins(self):
         """create the name of pins depend on the word size"""
         for i in range(self.word_size):

compiler/modules/wordline_driver.py

@@ -20,13 +20,14 @@ class wordline_driver(design.design):
         design.design.__init__(self, "wordline_driver")
 
         self.rows = rows
+        
         self.create_netlist()
         if not OPTS.netlist_only:
             self.create_layout()
 
     def create_netlist(self):
-        self.add_pins()
         self.add_modules()
+        self.add_pins()
         self.create_drivers()
         
     def create_layout(self):

compiler/modules/write_driver_array.py

@@ -15,21 +15,27 @@ class write_driver_array(design.design):
         design.design.__init__(self, "write_driver_array")
         debug.info(1, "Creating {0}".format(self.name))
 
-        from importlib import reload
-        c = reload(__import__(OPTS.write_driver))
-        self.mod_write_driver = getattr(c, OPTS.write_driver)
-        self.driver = self.mod_write_driver("write_driver")
-        self.add_mod(self.driver)
-
         self.columns = columns
         self.word_size = word_size
         self.words_per_row = int(columns / word_size)
 
-        self.width = self.columns * self.driver.width
-        self.height = self.height = self.driver.height
-        
         self.create_netlist()
-        self.create_layout()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+
+    def create_netlist(self):
+        self.add_modules()
+        self.add_pins()
+        self.create_write_array()
+        
+    def create_layout(self):
+        self.width = self.columns * self.driver.width
+        self.height = self.driver.height
+        
+        self.place_write_array()
+        self.add_layout_pins()
+        self.DRC_LVS()
 
     def add_pins(self):
         for i in range(self.word_size):
@@ -41,14 +47,12 @@ class write_driver_array(design.design):
         self.add_pin("vdd")
         self.add_pin("gnd")
 
-    def create_netlist(self):
-        self.add_pins()
-        self.create_write_array()
-        
-    def create_layout(self):
-        self.place_write_array()
-        self.add_layout_pins()
-        self.DRC_LVS()
+    def add_modules(self):
+        from importlib import reload
+        c = reload(__import__(OPTS.write_driver))
+        self.mod_write_driver = getattr(c, OPTS.write_driver)
+        self.driver = self.mod_write_driver("write_driver")
+        self.add_mod(self.driver)
 
     def create_write_array(self):
         self.driver_insts = {}