Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

compiler/tests/05_pbitcell_array_test.py

@@ -16,9 +16,6 @@ class pbitcell_array_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        global verify
-        import verify
-
         import bitcell_array
 
         debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")