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Two bank SRAMs working in both technologies.

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This commit is contained in:
Matt Guthaus
2017-09-29 16:22:13 -07:00
parent d29dd03373
commit e06e1691c8
41 changed files with 20945 additions and 19280 deletions
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compiler/tests/04_nor_2_test.py
+1 -1
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@@ -29,7 +29,7 @@ class nor_2_test(unittest.TestCase):
import tech
debug.info(2, "Checking 2-input nor gate")
tx = nor_2.nor_2(nmos_width=2 * tech.drc["minwidth_tx"])
tx = nor_2.nor_2()
self.local_check(tx)
OPTS.check_lvsdrc = True
compiler/tests/19_multi_bank_test.py
+5 -5
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@@ -25,20 +25,20 @@ class multi_bank_test(unittest.TestCase):
import bank
debug.info(1, "No column mux")
a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=2, name="test_bank1")
a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=2, name="bank1")
self.local_check(a)
debug.info(1, "Two way column mux")
a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=2, name="test_bank2")
self.local_check(a)
#a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=2, name="bank2")
#self.local_check(a)
debug.info(1, "Four way column mux")
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=2, name="test_bank3")
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=2, name="bank3")
self.local_check(a)
# Eight way has a short circuit of one column mux select to gnd rail
# debug.info(1, "Eight way column mux")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="test_bank4")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="bank4")
# self.local_check(a)
OPTS.check_lvsdrc = True
compiler/tests/19_single_bank_test.py
+4 -4
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@@ -26,20 +26,20 @@ class single_bank_test(unittest.TestCase):
import bank
debug.info(1, "No column mux")
a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="test_bank1")
a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="bank1")
self.local_check(a)
debug.info(1, "Two way column mux")
a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=1, name="test_bank2")
a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=1, name="bank2")
self.local_check(a)
debug.info(1, "Four way column mux")
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=1, name="test_bank3")
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=1, name="bank3")
self.local_check(a)
# Eight way has a short circuit of one column mux select to gnd rail
# debug.info(1, "Eight way column mux")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=1, name="test_bank4")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=1, name="bank4")
# self.local_check(a)
OPTS.check_lvsdrc = True
compiler/tests/20_sram_1bank_test.py
+4 -4
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@@ -26,19 +26,19 @@ class sram_1bank_test(unittest.TestCase):
import sram
debug.info(1, "Single bank, no column mux with control logic")
a = sram.sram(word_size=4, num_words=16, num_banks=1, name="test_sram1")
a = sram.sram(word_size=4, num_words=16, num_banks=1, name="sram1")
self.local_check(a)
debug.info(1, "Single bank two way column mux with control logic")
a = sram.sram(word_size=4, num_words=32, num_banks=1, name="test_sram2")
a = sram.sram(word_size=4, num_words=32, num_banks=1, name="sram2")
self.local_check(a)
debug.info(1, "Single bank, four way column mux with control logic")
a = sram.sram(word_size=4, num_words=64, num_banks=1, name="test_sram3")
a = sram.sram(word_size=4, num_words=64, num_banks=1, name="sram3")
self.local_check(a)
# debug.info(1, "Single bank, eight way column mux with control logic")
# a = sram.sram(word_size=2, num_words=128, num_banks=1, name="test_sram4")
# a = sram.sram(word_size=2, num_words=128, num_banks=1, name="sram4")
# self.local_check(a)
OPTS.check_lvsdrc = True
compiler/tests/20_sram_2bank_test.py
+4 -4
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@@ -26,19 +26,19 @@ class sram_2bank_test(unittest.TestCase):
import sram
debug.info(1, "Two bank, no column mux with control logic")
a = sram.sram(word_size=4, num_words=32, num_banks=2, name="test_sram1")
a = sram.sram(word_size=16, num_words=32, num_banks=2, name="sram1")
self.local_check(a)
debug.info(1, "Two bank two way column mux with control logic")
a = sram.sram(word_size=4, num_words=64, num_banks=2, name="test_sram2")
a = sram.sram(word_size=16, num_words=64, num_banks=2, name="sram2")
self.local_check(a)
debug.info(1, "Two bank, four way column mux with control logic")
a = sram.sram(word_size=4, num_words=128, num_banks=2, name="test_sram3")
a = sram.sram(word_size=16, num_words=128, num_banks=2, name="sram3")
self.local_check(a)
# debug.info(1, "Two bank, eight way column mux with control logic")
# a = sram.sram(word_size=2, num_words=256 num_banks=2, name="test_sram4")
# a = sram.sram(word_size=2, num_words=256 num_banks=2, name="sram4")
# self.local_check(a)
OPTS.check_lvsdrc = True
compiler/tests/20_sram_4bank_test.py
+4 -4
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@@ -26,19 +26,19 @@ class sram_4bank_test(unittest.TestCase):
import sram
debug.info(1, "Four bank, no column mux with control logic")
a = sram.sram(word_size=4, num_words=32, num_banks=4, name="test_sram1")
a = sram.sram(word_size=4, num_words=32, num_banks=4, name="sram1")
self.local_check(a)
debug.info(1, "Four bank two way column mux with control logic")
a = sram.sram(word_size=4, num_words=64, num_banks=4, name="test_sram2")
a = sram.sram(word_size=4, num_words=64, num_banks=4, name="sram2")
self.local_check(a)
debug.info(1, "Four bank, four way column mux with control logic")
a = sram.sram(word_size=4, num_words=128, num_banks=4, name="test_sram3")
a = sram.sram(word_size=4, num_words=128, num_banks=4, name="sram3")
self.local_check(a)
# debug.info(1, "Four bank, eight way column mux with control logic")
# a = sram.sram(word_size=2, num_words=256, num_banks=4, name="test_sram4")
# a = sram.sram(word_size=2, num_words=256, num_banks=4, name="sram4")
# self.local_check(a)
OPTS.check_lvsdrc = True
compiler/tests/21_hspice_delay_test.py
+19 -19
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@@ -32,7 +32,7 @@ class timing_sram_test(unittest.TestCase):
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
name="sram1")
OPTS.check_lvsdrc = True
@@ -52,25 +52,25 @@ class timing_sram_test(unittest.TestCase):
data = d.analyze(probe_address, probe_data,slews,loads)
if OPTS.tech_name == "freepdk45":
golden_data = {'read1_power': 0.017787999999999998,
'read0_power': 0.017827,
'write0_power': 0.016626,
'delay1': [0.02616],
'delay0': [0.10966999999999999],
'min_period': 0.264,
'write1_power': 0.015919000000000003,
'slew0': [0.027029],
'slew1': [0.021002999999999997]}
golden_data = {'read1_power': 0.025791799999999997,
'read0_power': 0.0260092,
'write0_power': 0.0241064,
'delay1': [0.0475006],
'delay0': [0.1380874],
'min_period': 0.322,
'write1_power': 0.024207199999999998,
'slew0': [0.026617000000000002],
'slew1': [0.0193804]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'read1_power': 4.5206,
'read0_power': 4.5492,
'write0_power': 3.8564,
'delay1': [0.5985562],
'delay0': [1.3725000000000003],
'min_period': 4.531,
'write1_power': 3.7291,
'slew0': [1.3013000000000001],
'slew1': [1.0045]}
golden_data = {'read1_power': 3.1765,
'read0_power': 3.1929,
'write0_power': 2.874,
'delay1': [0.8900045999999999],
'delay0': [1.9975000000000003],
'min_period': 5.781,
'write1_power': 2.6611,
'slew0': [1.2993000000000001],
'slew1': [0.9903856]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
compiler/tests/21_ngspice_delay_test.py
+19 -19
View File
@@ -30,7 +30,7 @@ class timing_sram_test(unittest.TestCase):
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
name="sram1")
import delay
@@ -48,25 +48,25 @@ class timing_sram_test(unittest.TestCase):
data = d.analyze(probe_address, probe_data,slews,loads)
if OPTS.tech_name == "freepdk45":
golden_data = {'read1_power': 0.022260799999999997,
'read0_power': 0.02274298,
'write0_power': 0.02000899,
'delay1': [0.026754629999999998],
'delay0': [0.1126814],
'min_period': 0.273,
'write1_power': 0.01934197,
'slew0': [0.02760651],
'slew1': [0.023076919999999997]}
golden_data = {'read1_power': 0.02527215,
'read0_power': 0.02573022,
'write0_power': 0.02237065,
'delay1': [0.04867785],
'delay0': [0.1423512],
'min_period': 0.332,
'write1_power': 0.02152122,
'slew0': [0.0273352],
'slew1': [0.021216870000000002]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'read1_power': 5.549996,
'read0_power': 4.781156,
'write0_power': 3.931431,
'delay1': [0.6227914],
'delay0': [1.414657],
'min_period': 4.688,
'write1_power': 3.409661,
'slew0': [1.345377],
'slew1': [1.05667]}
golden_data = {'read1_power': 3.244839,
'read0_power': 3.088234,
'write0_power': 2.6857420000000003,
'delay1': [0.9200643],
'delay0': [2.0509399999999998],
'min_period': 6.563,
'write1_power': 2.378355,
'slew0': [1.342019],
'slew1': [1.040885]}
else:
self.assertTrue(False) # other techs fail
compiler/tests/golden/sram_2_16_1_freepdk45.lef
+12573 -11847
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File diff suppressed because it is too large Load Diff
compiler/tests/golden/sram_2_16_1_freepdk45.lib
+21 -21
View File
@@ -74,7 +74,7 @@ cell (sram_2_16_1_freepdk45){
dont_use : true;
map_only : true;
dont_touch : true;
area : 799.659625;
area : 692.2795;
bus(DATA){
bus_type : DATA;
@@ -92,10 +92,10 @@ cell (sram_2_16_1_freepdk45){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0.020625");
values("0.0287643");
}
fall_power(scalar){
values("0.021124");
values("0.0284106");
}
}
timing(){
@@ -129,10 +129,10 @@ cell (sram_2_16_1_freepdk45){
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0.023099");
values("0.0320149");
}
fall_power(scalar){
values("0.023401");
values("0.0322925");
}
}
timing(){
@@ -140,24 +140,24 @@ cell (sram_2_16_1_freepdk45){
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.025, 0.026, 0.032",\
"0.026, 0.026, 0.033",\
"0.03, 0.031, 0.037");
values("0.046, 0.046, 0.053",\
"0.046, 0.047, 0.054",\
"0.051, 0.052, 0.059");
}
cell_fall(CELL_TABLE) {
values("0.11, 0.11, 0.118",\
"0.11, 0.111, 0.119",\
"0.114, 0.114, 0.122");
values("0.142, 0.143, 0.152",\
"0.143, 0.144, 0.152",\
"0.148, 0.149, 0.158");
}
rise_transition(CELL_TABLE) {
values("0.016, 0.017, 0.028",\
"0.016, 0.017, 0.028",\
"0.016, 0.018, 0.028");
values("0.014, 0.015, 0.027",\
"0.014, 0.015, 0.027",\
"0.014, 0.015, 0.027");
}
fall_transition(CELL_TABLE) {
values("0.02, 0.022, 0.037",\
"0.02, 0.022, 0.037",\
"0.021, 0.023, 0.037");
values("0.019, 0.02, 0.036",\
"0.019, 0.02, 0.036",\
"0.019, 0.02, 0.036");
}
}
}
@@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("0.166");
values("0.205");
}
fall_constraint(scalar) {
values("0.166");
values("0.205");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("0.332");
values("0.41");
}
fall_constraint(scalar) {
values("0.332");
values("0.41");
}
}
}
compiler/tests/golden/sram_2_16_1_freepdk45_analytical.lib
+7 -7
View File
@@ -74,7 +74,7 @@ cell (sram_2_16_1_freepdk45){
dont_use : true;
map_only : true;
dont_touch : true;
area : 799.659625;
area : 692.2795;
bus(DATA){
bus_type : DATA;
@@ -140,14 +140,14 @@ cell (sram_2_16_1_freepdk45){
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.12, 0.121, 0.131",\
"0.12, 0.121, 0.131",\
"0.12, 0.121, 0.131");
values("0.122, 0.123, 0.132",\
"0.122, 0.123, 0.132",\
"0.122, 0.123, 0.132");
}
cell_fall(CELL_TABLE) {
values("0.12, 0.121, 0.131",\
"0.12, 0.121, 0.131",\
"0.12, 0.121, 0.131");
values("0.122, 0.123, 0.132",\
"0.122, 0.123, 0.132",\
"0.122, 0.123, 0.132");
}
rise_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\
compiler/tests/golden/sram_2_16_1_scn3me_subm.lef
+7079 -6489
View File
File diff suppressed because it is too large Load Diff
compiler/tests/golden/sram_2_16_1_scn3me_subm.lib
+21 -21
View File
@@ -74,7 +74,7 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 102102.39;
area : 89304.3;
bus(DATA){
bus_type : DATA;
@@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("2.3875");
values("3.1588");
}
fall_power(scalar){
values("2.5832");
values("3.4922");
}
}
timing(){
@@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("2.9868");
values("3.9389");
}
fall_power(scalar){
values("3.0093");
values("3.9642");
}
}
timing(){
@@ -140,24 +140,24 @@ cell (sram_2_16_1_scn3me_subm){
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.261, 0.343, 1.013",\
"0.264, 0.345, 1.019",\
"0.311, 0.39, 1.062");
values("0.542, 0.626, 1.298",\
"0.545, 0.628, 1.304",\
"0.594, 0.674, 1.35");
}
cell_fall(CELL_TABLE) {
values("0.837, 0.945, 1.919",\
"0.841, 0.95, 1.925",\
"0.878, 0.986, 1.96");
values("1.532, 1.634, 2.6",\
"1.536, 1.639, 2.607",\
"1.587, 1.69, 2.657");
}
rise_transition(CELL_TABLE) {
values("0.21, 0.354, 1.887",\
"0.214, 0.356, 1.888",\
"0.313, 0.361, 1.889");
values("0.191, 0.337, 1.884",\
"0.193, 0.338, 1.885",\
"0.195, 0.341, 1.884");
}
fall_transition(CELL_TABLE) {
values("0.236, 0.445, 2.463",\
"0.236, 0.445, 2.462",\
"0.235, 0.445, 2.454");
values("0.255, 0.448, 2.467",\
"0.256, 0.447, 2.468",\
"0.256, 0.447, 2.454");
}
}
}
@@ -308,20 +308,20 @@ cell (sram_2_16_1_scn3me_subm){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("3.75");
values("4.5315");
}
fall_constraint(scalar) {
values("3.75");
values("4.5315");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("7.5");
values("9.063");
}
fall_constraint(scalar) {
values("7.5");
values("9.063");
}
}
}
compiler/tests/golden/sram_2_16_1_scn3me_subm_analytical.lib
+7 -7
View File
@@ -74,7 +74,7 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 102102.39;
area : 89304.3;
bus(DATA){
bus_type : DATA;
@@ -140,14 +140,14 @@ cell (sram_2_16_1_scn3me_subm){
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.57, 0.617, 1.058",\
"0.57, 0.617, 1.058",\
"0.57, 0.617, 1.058");
values("0.553, 0.6, 1.041",\
"0.553, 0.6, 1.041",\
"0.553, 0.6, 1.041");
}
cell_fall(CELL_TABLE) {
values("0.57, 0.617, 1.058",\
"0.57, 0.617, 1.058",\
"0.57, 0.617, 1.058");
values("0.553, 0.6, 1.041",\
"0.553, 0.6, 1.041",\
"0.553, 0.6, 1.041");
}
rise_transition(CELL_TABLE) {
values("0.024, 0.081, 0.61",\