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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
Two bank SRAMs working in both technologies.
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@@ -73,7 +73,7 @@ class delay():
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self.sf.write("* SRAM output loads\n")
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for i in range(self.word_size):
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self.sf.write("CD{0} D[{0}] 0 {1}f\n".format(i,load))
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self.sf.write("CD{0} d[{0}] 0 {1}f\n".format(i,load))
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# add access transistors for data-bus
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self.sf.write("* Transmission Gates for data-bus and control signals\n")
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@@ -85,12 +85,12 @@ class delay():
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if i == self.probe_data:
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stimuli.gen_data(stim_file=self.sf,
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clk_times=self.cycle_times,
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sig_name="DATA[{0}]".format(i),
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sig_name="data[{0}]".format(i),
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period=period,
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slew=slew)
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else:
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stimuli.gen_constant(stim_file=self.sf,
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sig_name="D[{0}]".format(i),
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sig_name="d[{0}]".format(i),
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v_val=self.gnd)
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stimuli.gen_addr(self.sf,
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@@ -127,7 +127,7 @@ class delay():
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self.sf.write("* Measure statements for delay and power\n")
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trig_name = "clk"
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targ_name = "{0}".format("D[{0}]".format(self.probe_data))
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targ_name = "{0}".format("d[{0}]".format(self.probe_data))
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trig_val = targ_val = 0.5 * self.vdd
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# add measure statments for delay0
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# delay the target to measure after the negetive edge
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@@ -181,13 +181,13 @@ def gen_csb(stim_file, clk_times, period, slew):
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""" Generates the PWL CSb signal"""
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# values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP
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values = [1, 0, 0, 0, 0, 0, 0, 0, 1]
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gen_pwl(stim_file, "CSb", clk_times, values, period, slew, 0.05)
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gen_pwl(stim_file, "csb", clk_times, values, period, slew, 0.05)
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def gen_web(stim_file, clk_times, period, slew):
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""" Generates the PWL WEb signal"""
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# values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP
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values = [1, 0, 0, 0, 1, 0, 0, 1, 1]
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gen_pwl(stim_file, "WEb", clk_times, values, period, slew, 0.05)
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gen_pwl(stim_file, "web", clk_times, values, period, slew, 0.05)
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values = [1, 0, 0, 0, 1, 0, 0, 1, 1]
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gen_pwl(stim_file, "acc_en", clk_times, values, period, slew, 0)
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@@ -198,7 +198,7 @@ def gen_oeb(stim_file, clk_times, period, slew):
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""" Generates the PWL WEb signal"""
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# values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP
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values = [1, 1, 1, 1, 0, 1, 1, 0, 1]
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gen_pwl(stim_file, "OEb", clk_times, values, period, slew, 0.05)
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gen_pwl(stim_file, "oeb", clk_times, values, period, slew, 0.05)
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