mirror of
https://github.com/VLSIDA/OpenRAM.git
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Abstract basic DRC checks
This commit is contained in:
Matt Guthaus
+128
-115
@@ -29,7 +29,28 @@ GDS["unit"] = (0.0005,1e-9)
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GDS["zoom"] = 0.05
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###################################################
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##GDS Layer Map
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# Interconnect stacks
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###################################################
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poly_stack = ("poly", "contact", "metal1")
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active_stack = ("active", "contact", "metal1")
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metal1_stack = ("metal1", "via1", "metal2")
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metal2_stack = ("metal2", "via2", "metal3")
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metal3_stack = ("metal3", "via3", "metal4")
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# The FEOL stacks get us up to metal1
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feol_stacks = [poly_stack,
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active_stack]
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# The BEOL stacks are metal1 and up
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beol_stacks = [metal1_stack,
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metal2_stack,
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metal3_stack]
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layer_stacks = feol_stacks + beol_stacks
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###################################################
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# GDS Layer Map
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###################################################
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# create the GDS layer map
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@@ -44,8 +65,7 @@ layer["vtg"] = (6, 0)
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layer["vth"] = (7, 0)
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layer["thkox"] = (8, 0)
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layer["poly"] = (9, 0)
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layer["active_contact"] = (10, 0)
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layer["poly_contact"] = (10, 0)
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layer["contact"] = (10, 0)
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layer["metal1"] = (11, 0)
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layer["via1"] = (12, 0)
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layer["metal2"] = (13, 0)
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@@ -69,11 +89,7 @@ layer["text"] = (239, 0)
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layer["boundary"]= (239, 0)
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###################################################
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##END GDS Layer Map
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###################################################
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###################################################
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##DRC/LVS Rules Setup
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# DRC/LVS Rules Setup
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###################################################
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#technology parameter
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@@ -105,18 +121,21 @@ drc["minlength_channel"] = 0.05
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# WELL.2 Minimum spacing of nwell/pwell at different potential
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drc["pwell_to_nwell"] = 0.225
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# WELL.3 Minimum spacing of nwell/pwell at the same potential
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drc["well_to_well"] = 0.135
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# WELL.4 Minimum width of nwell/pwell
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drc["minwidth_well"] = 0.2
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drc.add_layer("well",
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width = 0.2,
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spacing = 0.135)
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# POLY.1 Minimum width of poly
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drc["minwidth_poly"] = 0.05
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# POLY.2 Minimum spacing of poly AND active
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drc["poly_to_poly"] = 0.14
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drc.add_layer("poly",
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width = 0.05,
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spacing = 0.14)
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# POLY.3 Minimum poly extension beyond active
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drc["poly_extend_active"] = 0.055
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# Not a rule
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drc["poly_to_poly_contact"] = 0.075
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drc["poly_to_contact"] = 0.075
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# POLY.4 Minimum enclosure of active around gate
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drc["active_enclosure_gate"] = 0.07
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# POLY.5 Minimum spacing of field poly to active
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@@ -129,162 +148,164 @@ drc["minarea_poly"] = 0.0
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# ACTIVE.2 Minimum spacing of active
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drc["active_to_body_active"] = 0.08
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# ACTIVE.1 Minimum width of active
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drc["minwidth_active"] = 0.09
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# Not a rule
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drc["active_to_active"] = 0
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drc.add_layer("active",
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width = 0.09,
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spacing = 0)
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# ACTIVE.3 Minimum enclosure/spacing of nwell/pwell to active
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drc["well_enclosure_active"] = 0.055
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# Reserved for asymmetric enclosures
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drc["well_extend_active"] = 0.055
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# Not a rule
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drc["minarea_active"] = 0
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drc.add_enclosure("well",
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layer = "active",
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enclosure = 0.055)
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# IMPLANT.1 Minimum spacing of nimplant/ pimplant to channel
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drc["implant_to_channel"] = 0.07
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# Not a rule
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drc["implant_enclosure_active"] = 0
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drc.add_enclosure("implant",
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layer = "active",
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enclosure = 0)
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# Not a rule
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drc["implant_enclosure_contact"] = 0
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drc.add_enclosure("implant",
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layer = "contact",
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enclosure = 0)
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# IMPLANT.2 Minimum spacing of nimplant/ pimplant to contact
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drc["implant_to_contact"] = 0.025
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# IMPLANT.3 Minimum width/ spacing of nimplant/ pimplant
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drc["implant_to_implant"] = 0.045
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# IMPLANT.4 Minimum width/ spacing of nimplant/ pimplant
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drc["minwidth_implant"] = 0.045
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drc.add_layer("implant",
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width = 0.045,
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spacing = 0.045)
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# CONTACT.1 Minimum width of contact
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drc["minwidth_active_contact"] = 0.065
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# CONTACT.2 Minimum spacing of contact
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drc["active_contact_to_active_contact"] = 0.075
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drc.add_layer("contact",
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width = 0.065,
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spacing = 0.075)
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# CONTACT.4 Minimum enclosure of active around contact
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drc["active_enclosure_active_contact"] = 0.005
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# Reserved for asymmetric enclosures
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drc["active_extend_active_contact"] = 0.005
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drc.add_enclosure("active",
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layer = "contact",
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enclosure = 0.005)
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# CONTACT.6 Minimum spacing of contact and gate
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drc["active_contact_to_gate"] = 0.0375 #changed from 0.035
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drc["contact_to_gate"] = 0.0375 #changed from 0.035
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# CONTACT.7 Minimum spacing of contact and poly
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drc["active_contact_to_poly"] = 0.090
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drc["contact_to_poly"] = 0.090
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# CONTACT.1 Minimum width of contact
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drc["minwidth_poly_contact"] = 0.065
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# CONTACT.2 Minimum spacing of contact
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drc["poly_contact_to_poly_contact"] = 0.075
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# Reserved for asymmetric enclosures
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drc["poly_extend_contact"] = 0.005
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drc.add_layer("contact",
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width = 0.065,
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spacing = 0.075)
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# CONTACT.5 Minimum enclosure of poly around contact
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drc["poly_enclosure_poly_contact"] = 0.005
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# Reserved for asymmetric enclosures
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drc["poly_extend_poly_contact"] = 0.005
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drc.add_enclosure("poly",
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layer = "contact",
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enclosure = 0.005)
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# CONTACT.6 Minimum spacing of contact and gate
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drc["poly_contact_to_gate"] = 0.0375 #changed from 0.035
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drc["contact_to_gate"] = 0.0375 #changed from 0.035
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# CONTACT.7 Minimum spacing of contact and poly
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drc["poly_contact_to_poly"] = 0.090
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drc["contact_to_poly"] = 0.090
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# METAL1.1 Minimum width of metal1
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drc["minwidth_metal1"] = 0.065
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# METAL1.2 Minimum spacing of metal1
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drc["metal1_to_metal1"] = 0.065
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drc.add_layer("metal1",
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width = 0.065,
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spacing = 0.065)
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# METAL1.3 Minimum enclosure around contact on two opposite sides
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drc["metal1_enclosure_active_contact"] = 0
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# Reserved for asymmetric enclosures
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drc["metal1_extend_active_contact"] = 0.035
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# METAL1.3 Minimum enclosure around contact on two opposite sides
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drc["metal1_enclosure_poly_contact"] = 0
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# Reserved for asymmetric enclosures
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drc["metal1_extend_poly_contact"] = 0.035
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drc.add_enclosure("metal1",
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layer = "contact",
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enclosure = 0,
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extension = 0.035)
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# METAL1.4 inimum enclosure around via1 on two opposite sides
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drc["metal1_extend_via1"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal1_enclosure_via1"] = 0
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# Not a rule
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drc["minarea_metal1"] = 0
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drc.add_enclosure("metal1",
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layer = "via1",
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enclosure = 0,
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extension = 0.035)
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# VIA1.1 Minimum width of via1
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drc["minwidth_via1"] = 0.065
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# VIA1.2 Minimum spacing of via1
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drc["via1_to_via1"] = 0.075
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drc.add_layer("via1",
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width = 0.065,
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spacing = 0.075)
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# METALINT.1 Minimum width of intermediate metal
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drc["minwidth_metal2"] = 0.07
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# METALINT.2 Minimum spacing of intermediate metal
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drc["metal2_to_metal2"] = 0.07
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drc.add_layer("metal2",
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width = 0.07,
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spacing = 0.07)
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# METALINT.3 Minimum enclosure around via1 on two opposite sides
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drc["metal2_extend_via1"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via1"] = 0
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drc.add_enclosure("metal2",
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layer = "via1",
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enclosure = 0,
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extension = 0.035)
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# METALINT.4 Minimum enclosure around via[2-3] on two opposite sides
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drc["metal2_extend_via2"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via2"] = 0
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# Not a rule
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drc["minarea_metal2"] = 0
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drc.add_enclosure("metal2",
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layer = "via2",
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enclosure = 0,
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extension = 0.035)
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# VIA2-3.1 Minimum width of Via[2-3]
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drc["minwidth_via2"] = 0.065
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# VIA2-3.2 Minimum spacing of Via[2-3]
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drc["via2_to_via2"] = 0.075
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drc.add_layer("via2",
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width = 0.065,
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spacing = 0.075)
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# METALINT.1 Minimum width of intermediate metal
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drc["minwidth_metal3"] = 0.07
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# METALINT.2 Minimum spacing of intermediate metal
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#drc["metal3_to_metal3"] = 0.07
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# Minimum spacing of metal3 wider than 0.09 & longer than 0.3 = 0.09
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# Minimum spacing of metal3 wider than 0.27 & longer than 0.9 = 0.27
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# Minimum spacing of metal3 wider than 0.5 & longer than 1.8 = 0.5
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# Minimum spacing of metal3 wider than 0.9 & longer than 2.7 = 0.9
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# Minimum spacing of metal3 wider than 1.5 & longer than 4.0 = 1.5
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drc["metal3_to_metal3"] = drc_lut({(0.00, 0.0) : 0.07,
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(0.09, 0.3) : 0.09,
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(0.27, 0.9) : 0.27,
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(0.50, 1.8) : 0.5,
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(0.90, 2.7) : 0.9,
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(1.50, 4.0) : 1.5})
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drc.add_layer("metal3",
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width = 0.07,
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spacing = drc_lut({(0.00, 0.0) : 0.07,
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(0.09, 0.3) : 0.09,
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(0.27, 0.9) : 0.27,
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(0.50, 1.8) : 0.5,
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(0.90, 2.7) : 0.9,
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(1.50, 4.0) : 1.5}))
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# METALINT.3 Minimum enclosure around via1 on two opposite sides
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drc["metal3_extend_via2"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal3_enclosure_via2"] = 0
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drc.add_enclosure("metal3",
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layer = "via2",
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enclosure = 0,
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extension = 0.035)
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# METALINT.4 Minimum enclosure around via[2-3] on two opposite sides
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drc["metal3_extend_via3"]=0.035
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# Reserved for asymmetric enclosures
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drc["metal3_enclosure_via3"] = 0
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# Not a rule
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drc["minarea_metal3"] = 0
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drc.add_enclosure("metal3",
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layer = "via3",
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enclosure = 0,
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extension = 0.035)
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# VIA2-3.1 Minimum width of Via[2-3]
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drc["minwidth_via3"] = 0.07
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# VIA2-3.2 Minimum spacing of Via[2-3]
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drc["via3_to_via3"] = 0.085
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drc.add_layer("via3",
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width = 0.07,
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spacing = 0.085)
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# METALSMG.1 Minimum width of semi-global metal
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drc["minwidth_metal4"] = 0.14
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# METALSMG.2 Minimum spacing of semi-global metal
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#drc["metal4_to_metal4"] = 0.14
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# Minimum spacing of metal4 wider than 0.27 & longer than 0.9 = 0.27
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# Minimum spacing of metal4 wider than 0.5 & longer than 1.8 = 0.5
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# Minimum spacing of metal4 wider than 0.9 & longer than 2.7 = 0.9
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# Minimum spacing of metal4 wider than 1.5 & longer than 4.0 = 1.5
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drc["metal4_to_metal4"] = drc_lut({(0.00, 0.0) : 0.14,
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(0.27, 0.9) : 0.27,
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(0.50, 1.8) : 0.5,
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(0.90, 2.7) : 0.9,
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(1.50, 4.0) : 1.5})
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drc.add_layer("metal4",
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width = 0.14,
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spacing = drc_lut({(0.00, 0.0) : 0.14,
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(0.27, 0.9) : 0.27,
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(0.50, 1.8) : 0.5,
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(0.90, 2.7) : 0.9,
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(1.50, 4.0) : 1.5}))
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# METALSMG.3 Minimum enclosure around via[3-6] on two opposite sides
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drc["metal4_extend_via3"] = 0.0025
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# Reserved for asymmetric enclosure
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drc["metal4_enclosure_via3"] = 0.0025
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# Not a rule
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drc["minarea_metal4"] = 0
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drc.add_enclosure("metal4",
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layer = "via3",
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enclosure = 0.0025)
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# Metal 5-10 are ommitted
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###################################################
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##END DRC/LVS Rules
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###################################################
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###################################################
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##Spice Simulation Parameters
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# Spice Simulation Parameters
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###################################################
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#spice info
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@@ -347,11 +368,7 @@ parameter["sa_inv_nmos_size"] = 0.27 #micro-meters
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parameter["bitcell_drain_cap"] = 0.1 #In Femto-Farad, approximation of drain capacitance
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###################################################
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##END Spice Simulation Parameters
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###################################################
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###################################################
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##BEGIN Technology Tool Preferences
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# Technology Tool Preferences
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###################################################
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drc_name = "calibre"
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@@ -359,7 +376,3 @@ lvs_name = "calibre"
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pex_name = "calibre"
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blackbox_bitcell = False
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###################################################
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##END Technology Tool Preferences
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###################################################
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+115
-101
@@ -28,6 +28,27 @@ GDS["unit"]=(0.001,1e-6)
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# default label zoom
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GDS["zoom"] = 0.5
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###################################################
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# Interconnect stacks
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###################################################
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poly_stack = ("poly", "poly_contact", "metal1")
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active_stack = ("active", "active_contact", "metal1")
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metal1_stack = ("metal1", "via1", "metal2")
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metal2_stack = ("metal2", "via2", "metal3")
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metal3_stack = ("metal3", "via3", "metal4")
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# The FEOL stacks get us up to metal1
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feol_stacks = [poly_stack,
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active_stack]
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# The BEOL stacks are metal1 and up
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beol_stacks = [metal1_stack,
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metal2_stack,
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metal3_stack]
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layer_stacks = feol_stacks + beol_stacks
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###################################################
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##GDS Layer Map
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@@ -43,8 +64,8 @@ layer["active"] = (43, 0)
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layer["pimplant"] = (44, 0)
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layer["nimplant"] = (45, 0)
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layer["poly"] = (46, 0)
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layer["active_contact"] = (48, 0)
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layer["poly_contact"] = (47, 0)
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layer["active_contact"] = (48, 0)
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layer["metal1"] = (49, 0)
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layer["via1"] = (50, 0)
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layer["metal2"] = (51, 0)
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@@ -56,11 +77,7 @@ layer["text"] = (63, 0)
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layer["boundary"] = (63, 0)
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###################################################
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##END GDS Layer Map
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###################################################
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###################################################
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##DRC/LVS Rules Setup
|
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# DRC/LVS Rules Setup
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###################################################
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_lambda_ = 0.2
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@@ -90,163 +107,168 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
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drc["minwidth_tx"] = 4*_lambda_
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drc["minlength_channel"] = 2*_lambda_
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# 1.3 Minimum spacing between wells of same type (if both are drawn)
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drc["well_to_well"] = 6*_lambda_
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# 1.4 Minimum spacing between wells of different type (if both are drawn)
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drc["pwell_to_nwell"] = 0
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# 1.3 Minimum spacing between wells of same type (if both are drawn)
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# 1.1 Minimum width
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drc["minwidth_well"] = 12*_lambda_
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drc.add_layer("well",
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width = 12*_lambda_,
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spacing = 6*_lambda_)
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# 3.1 Minimum width
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drc["minwidth_poly"] = 2*_lambda_
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# 3.2 Minimum spacing over active
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drc["poly_to_poly"] = 3*_lambda_
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drc.add_layer("poly",
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width = 2*_lambda_,
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spacing = 3*_lambda_)
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# 3.3 Minimum gate extension of active
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drc["poly_extend_active"] = 2*_lambda_
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# 5.5.b Minimum spacing between poly contact and other poly (alternative rules)
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drc["poly_to_poly_contact"] = 4*_lambda_
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drc["poly_to_contact"] = 4*_lambda_
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# ??
|
||||
drc["active_enclosure_gate"] = 0.0
|
||||
# 3.5 Minimum field poly to active
|
||||
drc["poly_to_active"] = _lambda_
|
||||
# 3.2.a Minimum spacing over field poly
|
||||
drc["poly_to_field_poly"] = 3*_lambda_
|
||||
# Not a rule
|
||||
drc["minarea_poly"] = 0.0
|
||||
|
||||
# ??
|
||||
drc["active_to_body_active"] = 4*_lambda_ # Fix me
|
||||
# 2.1 Minimum width
|
||||
drc["minwidth_active"] = 3*_lambda_
|
||||
# 2.2 Minimum spacing
|
||||
drc["active_to_active"] = 3*_lambda_
|
||||
drc.add_layer("active",
|
||||
width = 3*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 2.3 Source/drain active to well edge
|
||||
drc["well_enclosure_active"] = 6*_lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["well_extend_active"] = 6*_lambda_
|
||||
# Not a rule
|
||||
drc["minarea_active"] = 0.0
|
||||
drc.add_enclosure("well",
|
||||
layer = "active",
|
||||
enclosure = 6*_lambda_)
|
||||
|
||||
# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width
|
||||
drc["implant_to_channel"] = 3*_lambda_
|
||||
# 4.2 Minimum select overlap of active
|
||||
drc["implant_enclosure_active"] = 2*_lambda_
|
||||
drc.add_enclosure("implant",
|
||||
layer = "active",
|
||||
enclosure = 2*_lambda_)
|
||||
# 4.3 Minimum select overlap of contact
|
||||
drc["implant_enclosure_contact"] = _lambda_
|
||||
drc.add_enclosure("implant",
|
||||
layer = "contact",
|
||||
enclosure = _lambda_)
|
||||
# Not a rule
|
||||
drc["implant_to_contact"] = 0
|
||||
# Not a rule
|
||||
drc["implant_to_implant"] = 0
|
||||
# Not a rule
|
||||
drc["minwidth_implant"] = 0
|
||||
drc.add_layer("implant",
|
||||
width = 0,
|
||||
spacing = 0)
|
||||
|
||||
# 6.1 Exact contact size
|
||||
drc["minwidth_active_contact"] = 2*_lambda_
|
||||
# 5.3 Minimum contact spacing
|
||||
drc["active_contact_to_active_contact"] = 3*_lambda_
|
||||
# 6.2.b Minimum active overlap
|
||||
drc["active_enclosure_active_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosure
|
||||
drc["active_extend_active_contact"] = _lambda_
|
||||
drc.add_layer("active_contact",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 6.2.b Minimum active overlap
|
||||
drc.add_enclosure("active",
|
||||
layer = "active_contact",
|
||||
enclosure = _lambda_)
|
||||
drc.add_enclosure("active",
|
||||
layer = "contact",
|
||||
enclosure = _lambda_)
|
||||
# Reserved for other technologies
|
||||
drc["active_contact_to_gate"] = 2*_lambda_
|
||||
drc["contact_to_gate"] = 2*_lambda_
|
||||
# 5.4 Minimum spacing to gate of transistor
|
||||
drc["active_contact_to_poly"] = 2*_lambda_
|
||||
drc["contact_to_poly"] = 2*_lambda_
|
||||
|
||||
# 6.1 Exact contact size
|
||||
drc["minwidth_poly_contact"] = 2*_lambda_
|
||||
# 5.3 Minimum contact spacing
|
||||
drc["poly_contact_to_poly_contact"] = 3*_lambda_
|
||||
drc.add_layer("poly_contact",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 5.2.b Minimum poly overlap
|
||||
drc["poly_enclosure_poly_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["poly_extend_poly_contact"] = _lambda_
|
||||
drc.add_enclosure("poly",
|
||||
layer = "poly_contact",
|
||||
enclosure = _lambda_)
|
||||
# Reserved for other technologies
|
||||
drc["poly_contact_to_gate"] = 2*_lambda_
|
||||
# 5.4 Minimum spacing to gate of transistor
|
||||
drc["poly_contact_to_poly"] = 2*_lambda_
|
||||
|
||||
# 7.1 Minimum width
|
||||
drc["minwidth_metal1"] = 3*_lambda_
|
||||
# 7.2 Minimum spacing
|
||||
drc["metal1_to_metal1"] = 3*_lambda_
|
||||
drc.add_layer("metal1",
|
||||
width = 3*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 7.3 Minimum overlap of any contact
|
||||
drc["metal1_enclosure_active_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosure
|
||||
drc["metal1_extend_active_contact"] = _lambda_
|
||||
# 7.3 Minimum overlap of any contact
|
||||
drc["metal1_enclosure_poly_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosure
|
||||
drc["metal1_extend_poly_contact"] = _lambda_
|
||||
# 8.3 Minimum overlap by metal1
|
||||
drc["metal1_enclosure_via1"] = _lambda_
|
||||
# Reserve for asymmetric enclosures
|
||||
drc["metal1_extend_via1"] = _lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal1"] = 0
|
||||
drc.add_enclosure("metal1",
|
||||
layer = "poly_contact",
|
||||
enclosure = _lambda_)
|
||||
drc.add_enclosure("metal1",
|
||||
layer = "active_contact",
|
||||
enclosure = _lambda_)
|
||||
# 8.3 Minimum overlap by metal1
|
||||
drc.add_enclosure("metal1",
|
||||
layer = "via1",
|
||||
enclosure = _lambda_)
|
||||
|
||||
# 8.1 Exact size
|
||||
drc["minwidth_via1"] = 2*_lambda_
|
||||
# 8.2 Minimum via1 spacing
|
||||
drc["via1_to_via1"] = 3*_lambda_
|
||||
drc.add_layer("via1",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
|
||||
# 9.1 Minimum width
|
||||
drc["minwidth_metal2"] = 3*_lambda_
|
||||
# 9.2 Minimum spacing
|
||||
drc["metal2_to_metal2"] = 3*_lambda_
|
||||
drc.add_layer("metal2",
|
||||
width = 3*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 9.3 Minimum overlap of via1
|
||||
drc["metal2_extend_via1"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal2_enclosure_via1"] = _lambda_
|
||||
drc.add_enclosure("metal2",
|
||||
layer = "via1",
|
||||
enclosure = _lambda_)
|
||||
# 14.3 Minimum overlap by metal2
|
||||
drc["metal2_extend_via2"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal2_enclosure_via2"] = _lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal2"] = 0
|
||||
drc.add_enclosure("metal2",
|
||||
layer = "via2",
|
||||
enclosure = _lambda_)
|
||||
|
||||
# 14.1 Exact size
|
||||
drc["minwidth_via2"] = 2*_lambda_
|
||||
# 14.2 Minimum spacing
|
||||
drc["via2_to_via2"] = 3*_lambda_
|
||||
drc.add_layer("via2",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
|
||||
# 15.1 Minimum width
|
||||
drc["minwidth_metal3"] = 3*_lambda_
|
||||
# 15.2 Minimum spacing to metal3
|
||||
drc["metal3_to_metal3"] = 3*_lambda_
|
||||
drc.add_layer("metal3",
|
||||
width = 3*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
|
||||
# 15.3 Minimum overlap of via 2
|
||||
drc["metal3_extend_via2"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal3_enclosure_via2"] = _lambda_
|
||||
drc.add_enclosure("metal3",
|
||||
layer = "via2",
|
||||
enclosure = _lambda_)
|
||||
|
||||
# 21.3 Minimum overlap by metal3
|
||||
drc["metal3_extend_via3"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal3_enclosure_via3"] = _lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal3"] = 0
|
||||
drc.add_enclosure("metal3",
|
||||
layer = "via3",
|
||||
enclosure = _lambda_)
|
||||
|
||||
# 21.1 Exact size
|
||||
drc["minwidth_via3"] = 2*_lambda_
|
||||
# 21.2 Minimum spacing
|
||||
drc["via3_to_via3"] = 3*_lambda_
|
||||
drc.add_layer("via3",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
|
||||
# 22.1 Minimum width
|
||||
drc["minwidth_metal4"] = 6*_lambda_
|
||||
# 22.2 Minimum spacing to metal4
|
||||
drc["metal4_to_metal4"] = 6*_lambda_
|
||||
drc.add_layer("metal4",
|
||||
width = 6*_lambda_,
|
||||
spacing = 6*_lambda_)
|
||||
|
||||
# 22.3 Minimum overlap of via 3
|
||||
drc["metal4_extend_via3"] = 2*_lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal4_enclosure_via3"] = 2*_lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal4"] = 0
|
||||
drc.add_enclosure("metal4",
|
||||
layer = "via3",
|
||||
enclosure = 2*_lambda_)
|
||||
|
||||
###################################################
|
||||
##END DRC/LVS Rules
|
||||
###################################################
|
||||
|
||||
###################################################
|
||||
##Spice Simulation Parameters
|
||||
# Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
# spice model info
|
||||
@@ -311,11 +333,7 @@ parameter["sa_inv_nmos_size"] = 9*_lambda_
|
||||
parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
###################################################
|
||||
##BEGIN Technology Tool Preferences
|
||||
# Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
drc_name = "magic"
|
||||
@@ -323,7 +341,3 @@ lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
blackbox_bitcell = False
|
||||
|
||||
###################################################
|
||||
##END Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
Reference in New Issue
Block a user