Merge branch 'tech_migration' into dev

compiler/tests/04_pand2_test.py

@@ -29,10 +29,6 @@ class pand2_test(openram_test):
         a = pand2.pand2(name="pand2x4", size=4)
         self.local_check(a)
 
-        debug.info(2, "Testing vertical pand2 gate 4x")
-        a = pand2.pand2(name="pand2x4", size=4, vertical=True)
-        self.local_check(a)
-        
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/04_pand3_test.py

@@ -29,10 +29,6 @@ class pand3_test(openram_test):
         a = pand3.pand3(name="pand3x4", size=4)
         self.local_check(a)
 
-        debug.info(2, "Testing vertical pand3 gate 4x")
-        a = pand3.pand3(name="pand3x4", size=4, vertical=True)
-        self.local_check(a)
-        
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/04_precharge_1rw_1r_test.py

@@ -0,0 +1,47 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class precharge_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        
+        # check precharge array in multi-port
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        debug.info(2, "Checking precharge for 1rw1r port 0")
+        tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(tx)
+
+        factory.reset()
+        debug.info(2, "Checking precharge for 1rw1r port 1")
+        tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
+        self.local_check(tx)
+
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/05_bitcell_array_1rw_1r_test.py

@@ -17,7 +17,7 @@ import debug
 
 #@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
 
-class bitcell_1rw_1r_array_test(openram_test):
+class bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/09_sense_amp_array_1rw_1r_test.py

@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class sense_amp_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
+        self.local_check(a)
+
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
+        self.local_check(a)
+
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/14_replica_bitcell_array_1rw_1r_test.py

@@ -13,7 +13,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class replica_bitcell_array_test(openram_test):
+class replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/14_replica_column_1rw_1r_test.py

@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California 
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class replica_column_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        debug.info(2, "Testing replica column for 6t_cell")
+        a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1)
+        self.local_check(a)
+
+        debug.info(2, "Testing replica column for 6t_cell")
+        a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=1, replica_bit=6)
+        self.local_check(a)
+        
+        debug.info(2, "Testing replica column for 6t_cell")
+        a = factory.create(module_type="replica_column", rows=4, left_rbl=2, right_rbl=0, replica_bit=2)
+        self.local_check(a)
+        
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py

@@ -15,7 +15,6 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-@unittest.skip("SKIPPING 20_psram_1bank_4mux_1rw_1r_test - Matt sucks, don't do this")
 class psram_1bank_4mux_1rw_1r_test(openram_test):
 
     def runTest(self):

compiler/tests/regress.py

@@ -22,14 +22,26 @@ header(__file__, OPTS.tech_name)
 # get a list of all files in the tests directory
 files = os.listdir(sys.path[0])
 
+# load a file with all tests to skip in a given technology
+# since tech_name is dynamically loaded, we can't use @skip directives
+try:
+    skip_file_name = "{0}/tests/skip_tests_{1}.txt".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
+    skip_file = open(skip_file_name, "r")
+    skip_tests = skip_file.read().splitlines()
+    for st in skip_tests:
+        debug.warning("Skipping: " + st)
+except FileNotFoundError:
+    skip_tests = []
+
 # assume any file that ends in "test.py" in it is a regression test
 nametest = re.compile("test\.py$", re.IGNORECASE)
-tests = list(filter(nametest.search, files))
-tests.sort()
+all_tests = list(filter(nametest.search, files))
+filtered_tests = list(filter(lambda i: i not in skip_tests, all_tests))
+filtered_tests.sort()
 
 # import all of the modules
 filenameToModuleName = lambda f: os.path.splitext(f)[0]
-moduleNames = map(filenameToModuleName, tests)
+moduleNames = map(filenameToModuleName, filtered_tests)
 modules = map(__import__, moduleNames)
 suite = unittest.TestSuite()
 load = unittest.defaultTestLoader.loadTestsFromModule

compiler/tests/skip_tests_s8.txt

@@ -0,0 +1,87 @@
+04_dummy_pbitcell_test.py
+04_pbitcell_test.py
+04_precharge_pbitcell_test.py
+04_replica_pbitcell_test.py
+04_single_level_column_mux_pbitcell_test.py
+05_bitcell_1rw_1r_array_test.py
+05_bitcell_array_test.py
+05_dummy_array_test.py
+05_pbitcell_array_test.py
+06_hierarchical_decoder_pbitcell_test.py
+06_hierarchical_decoder_test.py
+06_hierarchical_predecode2x4_pbitcell_test.py
+06_hierarchical_predecode2x4_test.py
+06_hierarchical_predecode3x8_pbitcell_test.py
+06_hierarchical_predecode3x8_test.py
+06_hierarchical_predecode4x16_test.py
+07_single_level_column_mux_array_pbitcell_test.py
+08_wordline_driver_array_pbitcell_test.py
+08_wordline_driver_array_test.py
+09_sense_amp_array_test_pbitcell.py
+09_sense_amp_array_test.py
+10_write_driver_array_pbitcell_test.py
+10_write_driver_array_test.py
+10_write_driver_array_wmask_pbitcell_test.py
+10_write_driver_array_wmask_test.py
+10_write_mask_and_array_pbitcell_test.py
+10_write_mask_and_array_test.py
+12_tri_gate_array_test.py
+14_replica_pbitcell_array_test.py
+14_replica_bitcell_array_test.py
+14_replica_column_test.py
+14_replica_column_1rw_1r_test.py
+18_port_address_test.py
+18_port_data_test.py
+18_port_data_wmask_test.py
+19_bank_select_pbitcell_test.py
+19_bank_select_test.py
+19_psingle_bank_test.py
+19_bank_select_pbitcell_test.py
+19_pmulti_bank_test.py
+19_multi_bank_test.py
+19_psingle_bank_test.py
+19_single_bank_1w_1r_test.py
+19_single_bank_wmask_1rw_1r_test.py
+19_single_bank_1rw_1r_test.py
+19_single_bank_test.py
+19_single_bank_wmask_test.py
+20_psram_1bank_2mux_1rw_1w_test.py
+20_psram_1bank_2mux_1rw_1w_wmask_test.py
+20_psram_1bank_2mux_1w_1r_test.py
+20_psram_1bank_2mux_test.py
+20_psram_1bank_4mux_1rw_1r_test.py
+20_sram_1bank_2mux_1w_1r_test.py
+20_sram_1bank_2mux_test.py
+20_sram_1bank_2mux_wmask_test.py
+20_sram_1bank_32b_1024_wmask_test.py
+20_sram_1bank_4mux_test.py
+20_sram_1bank_8mux_test.py
+20_sram_1bank_nomux_test.py
+20_sram_1bank_nomux_wmask_test.py
+20_sram_2bank_test.py
+21_hspice_delay_test.py
+21_hspice_setuphold_test.py
+21_model_delay_test.py
+21_ngspice_delay_test.py
+21_ngspice_setuphold_test.py
+22_psram_1bank_2mux_func_test.py
+22_psram_1bank_4mux_func_test.py
+22_psram_1bank_8mux_func_test.py
+22_psram_1bank_nomux_func_test.py
+22_sram_1bank_2mux_func_test.py
+22_sram_1bank_4mux_func_test.py
+22_sram_1bank_8mux_func_test.py
+22_sram_1bank_nomux_func_test.py
+22_sram_1rw_1r_1bank_nomux_func_test.py
+22_sram_wmask_func_test.py
+23_lib_sram_model_corners_test.py
+23_lib_sram_model_test.py
+23_lib_sram_prune_test.py
+23_lib_sram_test.py
+24_lef_sram_test.py
+25_verilog_sram_test.py
+26_hspice_pex_pinv_test.py
+26_ngspice_pex_pinv_test.py
+26_pex_test.py
+30_openram_back_end_test.py
+30_openram_front_end_test.py