mirror of https://github.com/VLSIDA/OpenRAM.git
Change lvs check to look only at the last/top module.
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@ -215,18 +215,26 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
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os.system(cmd)
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os.chdir(cwd)
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total_errors = 0
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# check the result for these lines in the summary:
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f = open(resultsfile, "r")
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results = f.readlines()
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f.close()
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# Look for the results after the final "Subcircuit summary:"
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# which will be the top-level netlist.
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final_results = []
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for line in reversed(results):
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if "Subcircuit summary:" in line:
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break
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else:
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final_results.insert(0,line)
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# Netlists do not match.
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test = re.compile("Netlists do not match.")
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incorrect = filter(test.search, results)
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# There were property errors.
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# There were property errors in any module.
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test = re.compile("Property errors were found.")
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propertyerrors = filter(test.search, results)
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total_errors += len(propertyerrors)
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# Require pins to match?
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# Cell pin lists for pnand2_1.spice and pnand2_1 altered to match.
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# test = re.compile(".*altered to match.")
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@ -234,17 +242,19 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
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# if len(pinerrors)>0:
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# debug.warning("Pins altered to match in {}.".format(cell_name))
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total_errors = len(propertyerrors) + len(incorrect)
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# If we want to ignore property errors
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#total_errors = len(incorrect)
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#if len(propertyerrors)>0:
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# debug.warning("Property errors found, but not checking them.")
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# Netlists do not match.
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test = re.compile("Netlists do not match.")
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incorrect = filter(test.search, final_results)
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total_errors += len(incorrect)
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# Netlists match uniquely.
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test = re.compile("Netlists match uniquely.")
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correct = filter(test.search, results)
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correct = filter(test.search, final_results)
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# Fail if they don't match. Something went wrong!
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if correct == 0:
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if len(correct) == 0:
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total_errors += 1
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if total_errors>0:
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