Merge branch 'dev' into automated_analytical_model

README.md

@@ -43,12 +43,12 @@ The OpenRAM compiler has very few dependencies:
 
 If you want to perform DRC and LVS, you will need either:
 + Calibre (for [FreePDK45])
-+ [Magic] 8.3.27 or higher (for [SCMOS])
++ [Magic] 8.3.130 or newer
-+ [Netgen] 1.5 (for [SCMOS])
++ [Netgen] 1.5.164 or newer
 
 You must set two environment variables: 
 + OPENRAM\_HOME should point to the compiler source directory. 
-+ OPENERAM\_TECH should point to a root technology directory.
++ OPENERAM\_TECH should point to one or more root technology directories (colon separated).
 
 ## Environment
 
@@ -65,11 +65,11 @@ You may also wish to add OPENRAM\_HOME to your PYTHONPATH:
   export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME"
 ```
 
-We include the tech files necessary for [SCMOS]
+We include the tech files necessary for [SCMOS] SCN4M_SUBM. The
-SCN4M_SUBM. The [SCMOS] spice models, however, are generic and should
+[SCMOS] spice models, however, are generic and should be replaced with
-be replaced with foundry models.  If you are using [FreePDK45], you
+foundry models.  If you are using [FreePDK45], you should also have
-should also have that set up and have the environment variable point
+that set up and have the environment variable point to the PDK. For
-to the PDK. For example add this to your .bashrc:
+example add this to your .bashrc:
 
 ```
   export FREEPDK45="/bsoe/software/design-kits/FreePDK45"
@@ -160,9 +160,9 @@ specific technology (e.g., [FreePDK45]) should be a subdirectory
   * dff.gds
   * sense_amp.gds
   * write_driver.gds
-  * cell_6t.gds
+  * cell_1rw.gds
-  * replica\_cell\_6t.gds 
+  * replica\_cell\_1rw.gds 
-  * dummy\_cell\_6t.gds 
+  * dummy\_cell\_1rw.gds 
 * sp_lib folder with all the .sp (premade) library netlists for the above cells.
 * layers.map 
 * A valid tech Python module (tech directory with \_\_init\_\_.py and tech.py) with:

compiler/base/channel_route.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/contact.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/delay_data.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/design.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -57,6 +57,12 @@ class design(hierarchy_design):
                                                   self.cell_name,
                                                   GDS["unit"])
 
+            # Convert names back to the original names
+            # so that copying will use the new names
+            for pin_name in self.pin_map:
+                for index1, pin in enumerate(self.pin_map[pin_name]):
+                    self.pin_map[pin_name][index1].name = self.get_original_pin_name(pin.name)
+
             self.width = width
             self.height = height
 

compiler/base/geometry.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/hierarchy_design.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/hierarchy_layout.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -1220,49 +1220,88 @@ class layout():
                                     pin.height())
 
             elif add_vias:
-                self.add_power_pin(name, pin.center(), start_layer=pin.layer)
+                self.copy_power_pin(pin)
 
-    def add_io_pin(self, instance, pin_name, new_name="", start_layer=None):
+    def add_io_pin(self, instance, pin_name, new_name, start_layer=None):
         """
         Add a signle input or output pin up to metal 3.
         """
         pin = instance.get_pin(pin_name)
 
-        if new_name == "":
-            new_name = pin_name
-
         if not start_layer:
             start_layer = pin.layer
-            
-        # Just use the power pin function for now to save code
-        self.add_power_pin(name=new_name, loc=pin.center(), start_layer=start_layer)
 
-    def add_power_pin(self, name, loc, size=[1, 1], directions=None, start_layer="m1"):
+        # Just use the power pin function for now to save code
+        self.add_power_pin(new_name, pin.center(), start_layer=start_layer)
+
+    def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
+        # Hack for min area
+        if OPTS.tech_name == "sky130":
+            min_area = drc["minarea_{}".format(self.pwr_grid_layer)]
+            width = round_to_grid(sqrt(min_area))
+            height = round_to_grid(min_area / width)
+        else:
+            width = None
+            height = None
+
+        if start_layer == self.pwr_grid_layer:
+            self.add_layout_pin_rect_center(text=name,
+                                            layer=self.pwr_grid_layer,
+                                            offset=loc,
+                                            width=width,
+                                            height=height)
+        else:
+            via = self.add_via_stack_center(from_layer=start_layer,
+                                            to_layer=self.pwr_grid_layer,
+                                            offset=loc,
+                                            directions=directions)
+
+            if not width:
+                width = via.width
+            if not height:
+                height = via.height
+            self.add_layout_pin_rect_center(text=name,
+                                            layer=self.pwr_grid_layer,
+                                            offset=loc,
+                                            width=width,
+                                            height=height)
+
+    def copy_power_pin(self, pin, loc=None, directions=None):
         """
         Add a single power pin from the lowest power_grid layer down to M1 (or li) at
         the given center location. The starting layer is specified to determine
         which vias are needed.
         """
 
-        if start_layer == self.pwr_grid_layer:
+        if not loc:
-            self.add_layout_pin_rect_center(text=name,
+            loc = pin.center()
-                                            layer=self.pwr_grid_layer,
+            
-                                            offset=loc)
+        # Hack for min area
+        if OPTS.tech_name == "sky130":
+            min_area = drc["minarea_{}".format(self.pwr_grid_layer)]
+            width = round_to_grid(sqrt(min_area))
+            height = round_to_grid(min_area / width)
         else:
-            via = self.add_via_stack_center(from_layer=start_layer,
+            width = None
+            height = None
+            
+        if pin.layer == self.pwr_grid_layer:
+            self.add_layout_pin_rect_center(text=pin.name,
+                                            layer=self.pwr_grid_layer,
+                                            offset=loc,
+                                            width=width,
+                                            height=height)
+        else:
+            via = self.add_via_stack_center(from_layer=pin.layer,
                                             to_layer=self.pwr_grid_layer,
-                                            size=size,
                                             offset=loc,
                                             directions=directions)
 
-            # Hack for min area
+            if not width:
-            if OPTS.tech_name == "sky130":
-                width = round_to_grid(sqrt(drc["minarea_m3"]))
-                height = round_to_grid(drc["minarea_m3"] / width)
-            else:
                 width = via.width
+            if not height:
                 height = via.height
-            self.add_layout_pin_rect_center(text=name,
+            self.add_layout_pin_rect_center(text=pin.name,
                                             layer=self.pwr_grid_layer,
                                             offset=loc,
                                             width=width,

compiler/base/hierarchy_spice.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/lef.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/pin_layout.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/power_data.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/route.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/utils.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/vector.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/verilog.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/wire.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/wire_path.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/wire_spice_model.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/bitcell_1port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/bitcell_2port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/bitcell_base.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/col_cap_bitcell_1port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/col_cap_bitcell_2port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/dummy_bitcell_1port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/dummy_bitcell_2port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/dummy_pbitcell.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/pbitcell.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/replica_bitcell_1port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/replica_bitcell_2port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/replica_pbitcell.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/row_cap_bitcell_1port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/bitcells/row_cap_bitcell_2port.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/__init__.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/bit_polarity.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/charutils.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/delay.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/functional.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/lib.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/logical_effort.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/measurements.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/model_check.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/setup_hold.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/simulation.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/sram_op.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/stimuli.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/trim_spice.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/custom/dff.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/custom/inv_dec.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/custom/nand2_dec.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/custom/nand3_dec.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/custom/nand4_dec.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/custom/sense_amp.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/custom/tri_gate.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/custom/write_driver.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/datasheet/add_db.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/datasheet/datasheet.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/datasheet/datasheet_gen.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/datasheet/table_gen.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/debug.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/design_rules.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/drc_lut.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/drc_value.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/gen_stimulus.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/globals.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/and2_dec.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/and3_dec.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/and4_dec.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/bank.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -615,9 +615,7 @@ class bank(design.design):
                 for pin_name in ["vdd", "gnd"]:
                     pin_list = inst.get_pins(pin_name)
                     for pin in pin_list:
-                        self.add_power_pin(pin_name,
+                        self.copy_power_pin(pin, pin.center())
-                                           pin.center(),
-                                           start_layer=pin.layer)
 
     def route_bank_select(self, port):
         """ Route the bank select logic. """

compiler/modules/bank_select.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/bitcell_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/bitcell_base_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/col_cap_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California
+# Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
 from bitcell_base_array import bitcell_base_array
@@ -100,7 +100,5 @@ class col_cap_array(bitcell_base_array):
                 inst = self.cell_inst[row, col]
                 for pin_name in ["vdd", "gnd"]:
                     for pin in inst.get_pins(pin_name):
-                        self.add_power_pin(name=pin_name,
+                        self.copy_power_pin(pin)
-                                           loc=pin.center(),
-                                           start_layer=pin.layer)
 

compiler/modules/column_mux_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/control_logic.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/delay_chain.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -177,14 +177,10 @@ class delay_chain(design.design):
             load_list = self.load_inst_map[inst]
             for pin_name in ["vdd", "gnd"]:
                 pin = load_list[0].get_pin(pin_name)
-                self.add_power_pin(pin_name,
+                self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
-                                   pin.rc() - vector(self.m1_pitch, 0),
-                                   start_layer=pin.layer)
 
                 pin = load_list[-2].get_pin(pin_name)
-                self.add_power_pin(pin_name,
+                self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
-                                   pin.rc() - vector(self.m1_pitch, 0),
-                                   start_layer=pin.layer)
 
     def add_layout_pins(self):
 

compiler/modules/dff_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -112,11 +112,11 @@ class dff_array(design.design):
             for col in range(self.columns):
                 # Continous vdd rail along with label.
                 vdd_pin=self.dff_insts[row, col].get_pin("vdd")
-                self.add_power_pin("vdd", vdd_pin.center(), start_layer=vdd_pin.layer)
+                self.copy_power_pin(vdd_pin)
 
                 # Continous gnd rail along with label.
                 gnd_pin=self.dff_insts[row, col].get_pin("gnd")
-                self.add_power_pin("gnd", gnd_pin.center(), start_layer=gnd_pin.layer)
+                self.copy_power_pin(gnd_pin)
 
         for row in range(self.rows):
             for col in range(self.columns):

compiler/modules/dff_buf.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/dff_buf_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -159,11 +159,11 @@ class dff_buf_array(design.design):
             for col in range(self.columns):
                 # Continous vdd rail along with label.
                 vdd_pin=self.dff_insts[row, col].get_pin("vdd")
-                self.add_power_pin("vdd", vdd_pin.lc(), start_layer=vdd_pin.layer)
+                self.copy_power_pin(vdd_pin, loc=vdd_pin.lc())
 
                 # Continous gnd rail along with label.
                 gnd_pin=self.dff_insts[row, col].get_pin("gnd")
-                self.add_power_pin("gnd", gnd_pin.lc(), start_layer=gnd_pin.layer)
+                self.copy_power_pin(gnd_pin, loc=gnd_pin.lc())
 
     def add_layout_pins(self):
 

compiler/modules/dff_inv.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/dff_inv_array.py

@@ -1,17 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 import debug
 import design
-from tech import drc
-from math import log
 from vector import vector
 from globals import OPTS
-import dff_inv
+from sram_factory import factory
+
 
 class dff_inv_array(design.design):
     """
@@ -130,12 +129,11 @@ class dff_inv_array(design.design):
             for col in range(self.columns):
                 # Adds power pin on left of row
                 vdd_pin=self.dff_insts[row,col].get_pin("vdd")
-                self.add_power_pin("vdd", vdd_pin.lc())
+                self.add_power_pin(vdd_pin, loc=vdd_pin.lc())
 
                 # Adds gnd pin on left of row
                 gnd_pin=self.dff_insts[row,col].get_pin("gnd")
-                self.add_power_pin("gnd", gnd_pin.lc())
+                self.add_power_pin(gnd_pin, loc=gnd_pin.lc())
-
 
         for row in range(self.rows):
             for col in range(self.columns):

compiler/modules/dummy_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California
+# Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
 from bitcell_base_array import bitcell_base_array

compiler/modules/global_bitcell_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/hierarchical_decoder.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -611,12 +611,7 @@ class hierarchical_decoder(design.design):
                 for i in self.and_inst[:-1]:
                     pins = i.get_pins(n)
                     for pin in pins:
-                        self.add_power_pin(name=n,
+                        self.copy_power_pin(pin, loc=pin.uc())
-                                           loc=pin.uc(),
-                                           start_layer=pin.layer)
-                        self.add_power_pin(name=n,
-                                           loc=pin.uc(),
-                                           start_layer=pin.layer)
 
                 for i in self.pre2x4_inst + self.pre3x8_inst:
                     self.copy_layout_pin(i, n)
@@ -628,9 +623,7 @@ class hierarchical_decoder(design.design):
                     # The nand and inv are the same height rows...
                     supply_pin = self.and_inst[row].get_pin(pin_name)
                     pin_pos = vector(xoffset, supply_pin.cy())
-                    self.add_power_pin(name=pin_name,
+                    self.copy_power_pin(supply_pin, loc=pin_pos)
-                                       loc=pin_pos,
-                                       start_layer=supply_pin.layer)
 
                 # Copy the pins from the predecoders
                 for pre in self.pre2x4_inst + self.pre3x8_inst + self.pre4x16_inst:

compiler/modules/hierarchical_predecode.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -330,12 +330,7 @@ class hierarchical_predecode(design.design):
                 for i in self.inv_inst[:-1:2] + self.and_inst[:-1:2]:
                     pins = i.get_pins(n)
                     for pin in pins:
-                        self.add_power_pin(name=n,
+                        self.copy_power_pin(pin, loc=pin.uc())
-                                           loc=pin.uc(),
-                                           start_layer=pin.layer)
-                        self.add_power_pin(name=n,
-                                           loc=pin.uc(),
-                                           start_layer=pin.layer)
 
         # In other techs, we are using standard cell decoder cells with horizontal power
         else:
@@ -353,9 +348,7 @@ class hierarchical_predecode(design.design):
                         for xoffset in [self.inv_inst[0].lx() - self.bus_space,
                                         self.and_inst[0].lx() - self.bus_space]:
                             pin_pos = vector(xoffset, and_pin.cy())
-                            self.add_power_pin(name=n,
+                            self.copy_power_pin(and_pin, loc=pin_pos)
-                                               loc=pin_pos,
-                                               start_layer=and_pin.layer)
 
 
 

compiler/modules/hierarchical_predecode2x4.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/hierarchical_predecode3x8.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/hierarchical_predecode4x16.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/local_bitcell_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -186,9 +186,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
             for inst in supply_insts:
                 pin_list = inst.get_pins(pin_name)
                 for pin in pin_list:
-                    self.add_power_pin(name=pin_name,
+                    self.copy_power_pin(pin)
-                                       loc=pin.center(),
-                                       start_layer=pin.layer)
 
     def route(self):
 

compiler/modules/module_type.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/multibank.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/orig_bitcell_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/port_address.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California
+# Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
 from math import log, ceil
@@ -82,9 +82,9 @@ class port_address(design.design):
 
         for rbl_vdd_pin in self.rbl_driver_inst.get_pins("vdd"):
             if layer_props.port_address.supply_offset:
-                self.add_power_pin("vdd", rbl_vdd_pin.center())
+                self.copy_power_pin(rbl_vdd_pin)
             else:
-                self.add_power_pin("vdd", rbl_vdd_pin.lc())
+                self.copy_power_pin(rbl_vdd_pin, loc=rbl_vdd_pin.lc())
 
         # Also connect the B input of the RBL and_dec to vdd
         if OPTS.local_array_size == 0:

compiler/modules/port_data.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California
+# Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
 from tech import drc

compiler/modules/precharge_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/modules/replica_bitcell_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California
+# Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
 
@@ -473,9 +473,7 @@ class replica_bitcell_array(bitcell_base_array):
             for inst in supply_insts:
                 pin_list = inst.get_pins(pin_name)
                 for pin in pin_list:
-                    self.add_power_pin(name=pin_name,
+                    self.copy_power_pin(pin)
-                                       loc=pin.center(),
-                                       start_layer=pin.layer)
 
             for inst in self.replica_col_insts:
                 if inst:

compiler/modules/replica_column.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California
+# Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
 import debug
@@ -190,7 +190,8 @@ class replica_column(bitcell_base_array):
         for (index, inst) in enumerate(self.cell_inst):
             for pin_name in ["vdd", "gnd"]:
                 if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
-                    self.copy_power_pins(inst, pin_name)
+                    for pin in inst.get_pins(pin_name):
+                        self.copy_power_pin(pin)
                 else:
                     self.copy_layout_pin(inst, pin_name)
 

compiler/modules/row_cap_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California
+# Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
 from bitcell_base_array import bitcell_base_array
@@ -113,7 +113,5 @@ class row_cap_array(bitcell_base_array):
                 inst = self.cell_inst[row, col]
                 for pin_name in ["vdd", "gnd"]:
                     for pin in inst.get_pins(pin_name):
-                        self.add_power_pin(name=pin_name,
+                        self.copy_power_pin(pin)
-                                           loc=pin.center(),
-                                           start_layer=pin.layer)
 

compiler/modules/sense_amp_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -146,16 +146,10 @@ class sense_amp_array(design.design):
             inst = self.local_insts[i]
 
             for gnd_pin in inst.get_pins("gnd"):
-                self.add_power_pin(name="gnd",
+                self.copy_power_pin(gnd_pin, directions=("V", "V"))
-                                   loc=gnd_pin.center(),
-                                   start_layer=gnd_pin.layer,
-                                   directions=("V", "V"))
 
             for vdd_pin in inst.get_pins("vdd"):
-                self.add_power_pin(name="vdd",
+                self.copy_power_pin(vdd_pin, directions=("V", "V"))
-                                   loc=vdd_pin.center(),
-                                   start_layer=vdd_pin.layer,
-                                   directions=("V", "V"))
 
             bl_pin = inst.get_pin(inst.mod.get_bl_names())
             br_pin = inst.get_pin(inst.mod.get_br_names())

compiler/modules/tri_gate_array.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.