Fix module import names for python3. Rename parse function to something meaningful.

compiler/characterizer/charutils.py

@@ -8,7 +8,7 @@ def relative_compare(value1,value2,error_tolerance=0.001):
     return (abs(value1 - value2) / max(value1,value2) <= error_tolerance)
 
 
-def parse_output(filename, key):
+def parse_spice_list(filename, key):
     """Parses a hspice output.lis file for a key value"""
     if OPTS.spice_name == "xa" :
         # customsim has a different output file name
@@ -22,6 +22,7 @@ def parse_output(filename, key):
     except IOError:
         debug.error("Unable to open spice output file: {0}".format(full_filename),1)
     contents = f.read()
+    f.close()
     # val = re.search(r"{0}\s*=\s*(-?\d+.?\d*\S*)\s+.*".format(key), contents)
     val = re.search(r"{0}\s*=\s*(-?\d+.?\d*[e]?[-+]?[0-9]*\S*)\s+.*".format(key), contents)
     

compiler/characterizer/delay.py

@@ -339,16 +339,16 @@ class delay():
         # Checking from not data_value to data_value
         self.write_delay_stimulus()
         self.stim.run_sim()
-        delay_hl = parse_output("timing", "delay_hl")
+        delay_hl = parse_spice_list("timing", "delay_hl")
-        delay_lh = parse_output("timing", "delay_lh")
+        delay_lh = parse_spice_list("timing", "delay_lh")
-        slew_hl = parse_output("timing", "slew_hl")
+        slew_hl = parse_spice_list("timing", "slew_hl")
-        slew_lh = parse_output("timing", "slew_lh")
+        slew_lh = parse_spice_list("timing", "slew_lh")
         delays = (delay_hl, delay_lh, slew_hl, slew_lh)
 
-        read0_power=parse_output("timing", "read0_power")
+        read0_power=parse_spice_list("timing", "read0_power")
-        write0_power=parse_output("timing", "write0_power")
+        write0_power=parse_spice_list("timing", "write0_power")
-        read1_power=parse_output("timing", "read1_power")
+        read1_power=parse_spice_list("timing", "read1_power")
-        write1_power=parse_output("timing", "write1_power")
+        write1_power=parse_spice_list("timing", "write1_power")
 
         if not self.check_valid_delays(delays):
             return (False,{})
@@ -378,13 +378,13 @@ class delay():
 
         self.write_power_stimulus(trim=False)
         self.stim.run_sim()
-        leakage_power=parse_output("timing", "leakage_power")
+        leakage_power=parse_spice_list("timing", "leakage_power")
         debug.check(leakage_power!="Failed","Could not measure leakage power.")
 
 
         self.write_power_stimulus(trim=True)
         self.stim.run_sim()
-        trim_leakage_power=parse_output("timing", "leakage_power")
+        trim_leakage_power=parse_spice_list("timing", "leakage_power")
         debug.check(trim_leakage_power!="Failed","Could not measure leakage power.")
 
         # For debug, you sometimes want to inspect each simulation.
@@ -473,10 +473,10 @@ class delay():
         # Checking from not data_value to data_value
         self.write_delay_stimulus()
         self.stim.run_sim()
-        delay_hl = parse_output("timing", "delay_hl")
+        delay_hl = parse_spice_list("timing", "delay_hl")
-        delay_lh = parse_output("timing", "delay_lh")
+        delay_lh = parse_spice_list("timing", "delay_lh")
-        slew_hl = parse_output("timing", "slew_hl")
+        slew_hl = parse_spice_list("timing", "slew_hl")
-        slew_lh = parse_output("timing", "slew_lh")
+        slew_lh = parse_spice_list("timing", "slew_lh")
         # if it failed or the read was longer than a period
         if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float:
             debug.info(2,"Invalid measures: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,

compiler/characterizer/setup_hold.py

@@ -186,8 +186,8 @@ class setup_hold():
                             target_time=feasible_bound, 
                             correct_value=correct_value)
         self.stim.run_sim()
-        ideal_clk_to_q = convert_to_float(parse_output("timing", "clk2q_delay"))
+        ideal_clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
-        setuphold_time = convert_to_float(parse_output("timing", "setup_hold_time"))
+        setuphold_time = convert_to_float(parse_spice_list("timing", "setup_hold_time"))
         debug.info(2,"*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode, correct_value,ideal_clk_to_q,setuphold_time))
 
         if type(ideal_clk_to_q)!=float or type(setuphold_time)!=float:
@@ -219,8 +219,8 @@ class setup_hold():
 
 
             self.stim.run_sim()
-            clk_to_q = convert_to_float(parse_output("timing", "clk2q_delay"))
+            clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
-            setuphold_time = convert_to_float(parse_output("timing", "setup_hold_time"))
+            setuphold_time = convert_to_float(parse_spice_list("timing", "setup_hold_time"))
             if type(clk_to_q)==float and (clk_to_q<1.1*ideal_clk_to_q) and type(setuphold_time)==float:
                 if mode == "SETUP": # SETUP is clk-din, not din-clk
                     setuphold_time *= -1e9

compiler/tests/21_hspice_delay_test.py

@@ -45,7 +45,7 @@ class timing_sram_test(openram_test):
         debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        d = delay.delay(s,tempspice,corner)
+        d = delay(s,tempspice,corner)
         import tech
         loads = [tech.spice["msflop_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]

compiler/tests/21_hspice_setuphold_test.py

@@ -33,7 +33,7 @@ class timing_setup_test(openram_test):
         slews = [tech.spice["rise_time"]*2]
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        sh = setup_hold.setup_hold(corner)
+        sh = setup_hold(corner)
         data = sh.analyze(slews,slews)
         #print data
         if OPTS.tech_name == "freepdk45":

compiler/tests/21_ngspice_delay_test.py

@@ -43,7 +43,7 @@ class timing_sram_test(openram_test):
         debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        d = delay.delay(s,tempspice,corner)
+        d = delay(s,tempspice,corner)
         import tech
         loads = [tech.spice["msflop_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]

compiler/tests/21_ngspice_setuphold_test.py

@@ -32,7 +32,7 @@ class timing_setup_test(openram_test):
         slews = [tech.spice["rise_time"]*2]
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        sh = setup_hold.setup_hold(corner)
+        sh = setup_hold(corner)
         data = sh.analyze(slews,slews)
         #print data
         if OPTS.tech_name == "freepdk45":