mirror of https://github.com/VLSIDA/OpenRAM.git
added the cell property definitions
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@ -27,10 +27,28 @@ File containing the process technology parameters for SCMOS 4m, 0.35um
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# For example: tech_modules['contact'] = 'contact_scn4m'
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tech_modules = d.module_type()
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tech_modules["bitcell_1port"] = "gf180_bitcell"
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###################################################
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# Custom cell properties
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###################################################
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cell_properties = d.cell_properties()
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cell_properties.bitcell_1port.port_order = ['BL', 'BR','GND', 'VDD', 'nwell', 'pwell', 'WL']
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cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER", "BIAS", "BIAS", "INPUT"]
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cell_properties.bitcell_1port.port_map = {'BL': 'BL',
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'BR': 'BR',
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'WL': 'WL',
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'VDD': 'VPWR',
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'pwell': 'VNB',
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'nwell': 'VPB',
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'GND': 'VGND'}
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cell_properties.bitcell_1port.wl_layer = "m3"
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cell_properties.bitcell_1port.bl_layer = "m2"
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cell_properties.bitcell_1port.vdd_layer = "m1"
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cell_properties.bitcell_1port.gnd_layer = "m1"
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cell_properties.ptx.model_is_subckt = True
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###################################################
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