mirror of https://github.com/VLSIDA/OpenRAM.git
merge in opc fixes
This commit is contained in:
commit
de60a1c38a
|
|
@ -42,6 +42,7 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
|
||||||
self.strap = factory.create(module_type="internal", version="wlstrap")
|
self.strap = factory.create(module_type="internal", version="wlstrap")
|
||||||
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
||||||
self.strap3 = factory.create(module_type="internal", version="wlstrapa")
|
self.strap3 = factory.create(module_type="internal", version="wlstrapa")
|
||||||
|
self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
|
||||||
|
|
||||||
def create_instances(self):
|
def create_instances(self):
|
||||||
""" Create the module instances used in this design """
|
""" Create the module instances used in this design """
|
||||||
|
|
@ -66,10 +67,14 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
|
||||||
self.connect_inst(self.get_bitcell_pins(row, col))
|
self.connect_inst(self.get_bitcell_pins(row, col))
|
||||||
if col != self.column_size - 1:
|
if col != self.column_size - 1:
|
||||||
if alternate_strap:
|
if alternate_strap:
|
||||||
name="row_{}_col_{}_wlstrap_p".format(row, col)
|
if row % 2:
|
||||||
row_layout.append(self.strap2)
|
row_layout.append(self.strap4)
|
||||||
self.add_inst(name=name.format(row, col),
|
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
|
||||||
mod=self.strap2)
|
mod=self.strap4)
|
||||||
|
else:
|
||||||
|
row_layout.append(self.strap2)
|
||||||
|
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
|
||||||
|
mod=self.strap2)
|
||||||
alternate_strap = 0
|
alternate_strap = 0
|
||||||
else:
|
else:
|
||||||
if row % 2:
|
if row % 2:
|
||||||
|
|
|
||||||
|
|
@ -48,6 +48,8 @@ class sky130_dummy_array(sky130_bitcell_base_array):
|
||||||
self.dummy_cell2 = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a")
|
self.dummy_cell2 = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a")
|
||||||
self.strap = factory.create(module_type="internal", version="wlstrap")
|
self.strap = factory.create(module_type="internal", version="wlstrap")
|
||||||
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
||||||
|
self.strap3 = factory.create(module_type="internal", version="wlstrapa")
|
||||||
|
self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
|
||||||
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
||||||
|
|
||||||
def create_instances(self):
|
def create_instances(self):
|
||||||
|
|
@ -73,16 +75,24 @@ class sky130_dummy_array(sky130_bitcell_base_array):
|
||||||
self.connect_inst(self.get_bitcell_pins(row, col))
|
self.connect_inst(self.get_bitcell_pins(row, col))
|
||||||
if col != self.column_size - 1:
|
if col != self.column_size - 1:
|
||||||
if alternate_strap:
|
if alternate_strap:
|
||||||
name = "row_{}_col_{}_wlstrap_p".format(row, col)
|
if col % 2:
|
||||||
row_layout.append(self.strap2)
|
row_layout.append(self.strap4)
|
||||||
self.add_inst(name=name,
|
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
|
||||||
mod=self.strap2)
|
mod=self.strap4)
|
||||||
|
else:
|
||||||
|
row_layout.append(self.strap4)
|
||||||
|
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
|
||||||
|
mod=self.strap4)
|
||||||
alternate_strap = 0
|
alternate_strap = 0
|
||||||
else:
|
else:
|
||||||
name="row_{}_col_{}_wlstrap".format(row, col)
|
if col % 2:
|
||||||
row_layout.append(self.strap)
|
row_layout.append(self.strap)
|
||||||
self.add_inst(name=name,
|
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
|
||||||
mod=self.strap)
|
mod=self.strap)
|
||||||
|
else:
|
||||||
|
row_layout.append(self.strap3)
|
||||||
|
self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
|
||||||
|
mod=self.strap3)
|
||||||
alternate_strap = 1
|
alternate_strap = 1
|
||||||
self.connect_inst(self.get_strap_pins(row, col, name))
|
self.connect_inst(self.get_strap_pins(row, col, name))
|
||||||
if alternate_bitcell == 0:
|
if alternate_bitcell == 0:
|
||||||
|
|
|
||||||
|
|
@ -22,6 +22,8 @@ class sky130_internal(design.design):
|
||||||
self.name = "sky130_fd_bd_sram__sram_sp_wlstrap_p"
|
self.name = "sky130_fd_bd_sram__sram_sp_wlstrap_p"
|
||||||
elif version == "wlstrapa":
|
elif version == "wlstrapa":
|
||||||
self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa"
|
self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa"
|
||||||
|
elif version == "wlstrapa_p":
|
||||||
|
self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa_p"
|
||||||
else:
|
else:
|
||||||
debug.error("Invalid version", -1)
|
debug.error("Invalid version", -1)
|
||||||
design.design.__init__(self, name=self.name)
|
design.design.__init__(self, name=self.name)
|
||||||
|
|
|
||||||
|
|
@ -100,6 +100,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
|
||||||
|
|
||||||
self.strap1 = factory.create(module_type="internal", version="wlstrap")
|
self.strap1 = factory.create(module_type="internal", version="wlstrap")
|
||||||
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
||||||
|
self.strap3 = factory.create(module_type="internal", version="wlstrapa_p")
|
||||||
|
|
||||||
self.colend = factory.create(module_type="col_cap", version="colend")
|
self.colend = factory.create(module_type="col_cap", version="colend")
|
||||||
self.edge_cell = self.colend
|
self.edge_cell = self.colend
|
||||||
|
|
@ -132,9 +133,9 @@ class sky130_replica_column(sky130_bitcell_base_array):
|
||||||
row_layout.append(self.replica_cell2)
|
row_layout.append(self.replica_cell2)
|
||||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell2)
|
self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell2)
|
||||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||||
row_layout.append(self.strap2)
|
row_layout.append(self.strap3)
|
||||||
self.add_inst(name=name + "_strap_p", mod=self.strap2)
|
self.add_inst(name=name + "_strap", mod=self.strap3)
|
||||||
self.connect_inst(self.get_strap_pins(row, 0, name + "_strap_p"))
|
self.connect_inst(self.get_strap_pins(row, 0))
|
||||||
alternate_bitcell = 0
|
alternate_bitcell = 0
|
||||||
|
|
||||||
elif (row == 0):
|
elif (row == 0):
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue