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fix single port bitcell pattern

This commit is contained in:
jcirimel 2020-09-22 15:08:53 -07:00
parent 559dfbc7a6
commit de33ab3761
1 changed files with 8 additions and 3 deletions
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11
compiler/modules/bitcell_array.py
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@ -82,23 +82,24 @@ class bitcell_array(bitcell_base_array):
self.connect_inst(self.get_bitcell_pins(row, col)) self.connect_inst(self.get_bitcell_pins(row, col))
else: else:
self.array_layout = [] self.array_layout = []
alternate_bitcell = 0
for row in range(0,self.row_size): for row in range(0,self.row_size):
row_layout = [] row_layout = []
alternate_bitcell = 1
alternate_strap = 1 alternate_strap = 1
for col in range(0,self.column_size): for col in range(0,self.column_size):
if alternate_bitcell == 1: if alternate_bitcell == 1:
row_layout.append(self.cell) row_layout.append(self.cell)
self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col), self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
mod=self.cell) mod=self.cell)
alternate_bitcell = 0
else: else:
row_layout.append(self.cell2) row_layout.append(self.cell2)
self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col), self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
mod=self.cell2) mod=self.cell2)
alternate_bitcell = 1
self.connect_inst(self.get_bitcell_pins(row, col)) self.connect_inst(self.get_bitcell_pins(row, col))
if col != self.column_size-1: if col != self.column_size-1:
if alternate_strap: if alternate_strap:
@ -113,6 +114,10 @@ class bitcell_array(bitcell_base_array):
mod=self.strap) mod=self.strap)
alternate_strap = 1 alternate_strap = 1
self.connect_inst([]) self.connect_inst([])
if alternate_bitcell == 0:
alternate_bitcell = 1
else:
alternate_bitcell = 0
self.array_layout.append(row_layout) self.array_layout.append(row_layout)
def analytical_power(self, corner, load): def analytical_power(self, corner, load):