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OpenRAM
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move vdd pins around to make routing nice

This commit is contained in:
SWalker 2023-09-14 21:33:49 -07:00
parent 5c22e382b5
commit ddba3b3718
3 changed files with 16 additions and 10 deletions
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13
compiler/modules/rom_address_control_array.py
View File

@ -119,4 +119,15 @@ class rom_address_control_array(design):
for pin in tmp_pins:
self.copy_layout_pin(self, "vdd_edge", "vdd")
self.remove_layout_pin("vdd_edge")
self.remove_layout_pin("vdd_edge")
tmp_pins = []
for pin in self.get_pins("gnd"):
edge = vector(pin.rx() + 0.5 * self.route_width, pin.cy())
tmp_pins.append(self.add_layout_pin_rect_center("gnd_edge", layer=self.route_layer, offset=edge))
self.copy_layout_pin_shapes("gnd")
self.remove_layout_pin("gnd")
for pin in tmp_pins:
self.copy_layout_pin(self, "gnd_edge", "gnd")
self.remove_layout_pin("gnd_edge")

3
compiler/modules/rom_address_control_buf.py
View File

@ -127,8 +127,6 @@ class rom_address_control_buf(design):
poly_y = A_out.cy()
contact_offset = vector(ppoly_center, clk2_pin.cy())
self.add_layout_pin_rect_center("cont", offset=contact_offset, layer="poly")
self.add_layout_pin_rect_center("ppoly", offset=vector(ppoly_center, poly_y), layer="poly")
# Route the two shared clk inputs together by connecting poly
self.add_segment_center("poly", contact_offset, vector(ppoly_center, poly_y))
@ -180,7 +178,6 @@ class rom_address_control_buf(design):
left_edge = self.inv_inst.get_pin("Z").cx() - 2 * self.contact_width - 2 * self.active_contact_to_gate - 4 * self.active_enclose_contact - self.poly_width - self.active_space
contact_pos = vector(left_edge, source_pin.cy())
self.add_layout_pin_rect_center("left_edge", offset=contact_pos, layer="m1")
self.add_via_center(layers=self.active_stack,
offset=contact_pos,
implant_type="n",

10
compiler/modules/rom_wordline_driver_array.py
View File

@ -88,8 +88,6 @@ class rom_wordline_driver_array(design):
Add a pin for each row of vdd/gnd which
are must-connects next level up.
"""
# self.route_vertical_pins("vdd", self.wld_inst, xside="cx", layer=self.supply_layer)
# self.route_vertical_pins("gnd", self.wld_inst, xside="cx", layer=self.supply_layer)
if not self.invert_outputs:
vdd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("vdd")]
gnd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("gnd")]
@ -110,13 +108,13 @@ class rom_wordline_driver_array(design):
# Place the top level supply pins on the edge of the module
for pin in self.get_pins("gnd_tmp"):
bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width)
top = vector(pin.cx(), pin.uy() + 0.5 * supply_width)
bottom = vector(pin.cx(), pin.by())
top = vector(pin.cx(), pin.uy())
self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="gnd")
for pin in self.get_pins("vdd_tmp"):
bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width)
top = vector(pin.cx(), pin.uy() + 0.5 * supply_width)
bottom = vector(pin.cx(), pin.by())
top = vector(pin.cx(), pin.uy())
self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="vdd")