mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 08:27:11 +02:00
move vdd pins around to make routing nice
This commit is contained in:
@@ -88,8 +88,6 @@ class rom_wordline_driver_array(design):
|
||||
Add a pin for each row of vdd/gnd which
|
||||
are must-connects next level up.
|
||||
"""
|
||||
# self.route_vertical_pins("vdd", self.wld_inst, xside="cx", layer=self.supply_layer)
|
||||
# self.route_vertical_pins("gnd", self.wld_inst, xside="cx", layer=self.supply_layer)
|
||||
if not self.invert_outputs:
|
||||
vdd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("vdd")]
|
||||
gnd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("gnd")]
|
||||
@@ -110,13 +108,13 @@ class rom_wordline_driver_array(design):
|
||||
|
||||
# Place the top level supply pins on the edge of the module
|
||||
for pin in self.get_pins("gnd_tmp"):
|
||||
bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width)
|
||||
top = vector(pin.cx(), pin.uy() + 0.5 * supply_width)
|
||||
bottom = vector(pin.cx(), pin.by())
|
||||
top = vector(pin.cx(), pin.uy())
|
||||
self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="gnd")
|
||||
|
||||
for pin in self.get_pins("vdd_tmp"):
|
||||
bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width)
|
||||
top = vector(pin.cx(), pin.uy() + 0.5 * supply_width)
|
||||
bottom = vector(pin.cx(), pin.by())
|
||||
top = vector(pin.cx(), pin.uy())
|
||||
self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="vdd")
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user