Changes to allow decoder height to be a 2x multiple of bitcell height.

Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.

compiler/modules/bitcell_base_array.py

@@ -104,9 +104,9 @@ class bitcell_base_array(design.design):
         # For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space
         # Default uses prefered directions for each layer; this cell property is only currently used by s8 tech (03/20)
         try:
-            force_power_pins_vertical = cell_properties.bitcell_force_power_pins_vertical
+            bitcell_power_pin_directions = cell_properties.bitcell_power_pin_directions
         except AttributeError:
-            force_power_pins_vertical = None
+            bitcell_power_pin_directions = None
 
         # Add vdd/gnd via stacks
         for row in range(self.row_size):
@@ -114,7 +114,10 @@ class bitcell_base_array(design.design):
                 inst = self.cell_inst[row,col]
                 for pin_name in ["vdd", "gnd"]:
                     for pin in inst.get_pins(pin_name):
-                        self.add_power_pin(name=pin_name, loc=pin.center(), vertical=force_power_pins_vertical, start_layer=pin.layer)
+                        self.add_power_pin(name=pin_name,
+                                           loc=pin.center(),
+                                           directions=bitcell_power_pin_directions,
+                                           start_layer=pin.layer)
 
     def _adjust_x_offset(self, xoffset, col, col_offset):
         tempx = xoffset