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OpenRAM
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Changed routing to allow for 2 write port with write mask.

This commit is contained in:
jsowash 2019-09-03 14:43:03 -07:00
parent 01bdea23ae
commit dd67490823
4 changed files with 67 additions and 47 deletions
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2
compiler/modules/bank.py
View File

@ -74,6 +74,8 @@ class bank(design.design):
# Remember the bank center for further placement # Remember the bank center for further placement
self.bank_array_ll = self.offset_all_coordinates().scale(-1,-1) self.bank_array_ll = self.offset_all_coordinates().scale(-1,-1)
self.bank_array_ur = self.bitcell_array_inst.ur() self.bank_array_ur = self.bitcell_array_inst.ur()
self.bank_array_ul = self.bitcell_array_inst.ul()
self.DRC_LVS() self.DRC_LVS()

11
compiler/modules/port_data.py
View File

@ -22,7 +22,7 @@ class port_data(design.design):
sram_config.set_local_config(self) sram_config.set_local_config(self)
self.port = port self.port = port
if self.write_size: if self.write_size is not None:
self.num_wmasks = int(self.word_size/self.write_size) self.num_wmasks = int(self.word_size/self.write_size)
else: else:
self.num_wmasks = 0 self.num_wmasks = 0
@ -58,7 +58,7 @@ class port_data(design.design):
if self.write_driver_array: if self.write_driver_array:
self.create_write_driver_array() self.create_write_driver_array()
if self.write_size: if self.write_size is not None:
self.create_write_mask_and_array() self.create_write_mask_and_array()
else: else:
self.write_mask_and_array_inst = None self.write_mask_and_array_inst = None
@ -187,11 +187,12 @@ class port_data(design.design):
word_size=self.word_size, word_size=self.word_size,
write_size=self.write_size) write_size=self.write_size)
self.add_mod(self.write_driver_array) self.add_mod(self.write_driver_array)
if self.write_size: if self.write_size is not None:
self.write_mask_and_array = factory.create(module_type="write_mask_and_array", self.write_mask_and_array = factory.create(module_type="write_mask_and_array",
columns=self.num_cols, columns=self.num_cols,
word_size=self.word_size, word_size=self.word_size,
write_size=self.write_size) write_size=self.write_size,
port = self.port)
self.add_mod(self.write_mask_and_array) self.add_mod(self.write_mask_and_array)
else: else:
self.write_mask_and_array = None self.write_mask_and_array = None
@ -320,7 +321,7 @@ class port_data(design.design):
temp.append(self.bl_names[self.port] + "_out_{0}".format(bit)) temp.append(self.bl_names[self.port] + "_out_{0}".format(bit))
temp.append(self.br_names[self.port] + "_out_{0}".format(bit)) temp.append(self.br_names[self.port] + "_out_{0}".format(bit))
if self.write_size: if self.write_size is not None:
for i in range(self.num_wmasks): for i in range(self.num_wmasks):
temp.append("wdriver_sel_{}".format(i)) temp.append("wdriver_sel_{}".format(i))
else: else:

22
compiler/modules/write_mask_and_array.py
View File

@ -20,7 +20,7 @@ class write_mask_and_array(design.design):
The write mask AND array goes between the write driver array and the sense amp array. The write mask AND array goes between the write driver array and the sense amp array.
""" """
def __init__(self, name, columns, word_size, write_size): def __init__(self, name, columns, word_size, write_size, port):
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name)) debug.info(1, "Creating {0}".format(self.name))
self.add_comment("columns: {0}".format(columns)) self.add_comment("columns: {0}".format(columns))
@ -30,6 +30,7 @@ class write_mask_and_array(design.design):
self.columns = columns self.columns = columns
self.word_size = word_size self.word_size = word_size
self.write_size = write_size self.write_size = write_size
self.port = port
self.words_per_row = int(columns / word_size) self.words_per_row = int(columns / word_size)
self.num_wmasks = int(word_size / write_size) self.num_wmasks = int(word_size / write_size)
@ -106,13 +107,24 @@ class write_mask_and_array(design.design):
self.nand2 = factory.create(module_type="pnand2") self.nand2 = factory.create(module_type="pnand2")
supply_pin=self.nand2.get_pin("vdd") supply_pin=self.nand2.get_pin("vdd")
# Create the enable pin that connects all write mask AND array's B pins # Create the enable pin that connects all write mask AND array's B pins
beg_en_pin = self.and2_insts[0].get_pin("B") beg_en_pin = self.and2_insts[0].get_pin("B")
end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B") end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B")
self.add_layout_pin(text="en", if self.port == 0:
layer="metal3", self.add_layout_pin(text="en",
offset=beg_en_pin.bc(), layer="metal3",
width = end_en_pin.cx() - beg_en_pin.cx()) offset=beg_en_pin.bc(),
width=end_en_pin.cx() - beg_en_pin.cx())
else:
en_to_edge = self.and2.width - beg_en_pin.cx()
self.add_layout_pin(text="en",
layer="metal3",
offset=beg_en_pin.bc(),
width=end_en_pin.cx() - beg_en_pin.cx() + en_to_edge)
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
for i in range(self.num_wmasks): for i in range(self.num_wmasks):
# Copy remaining layout pins # Copy remaining layout pins

17
compiler/sram/sram_1bank.py
View File

@ -138,7 +138,7 @@ class sram_1bank(sram_base):
if port in self.write_ports: if port in self.write_ports:
if self.write_size: if self.write_size:
# Add the write mask flops below the write mask AND array. # Add the write mask flops below the write mask AND array.
wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.wmask_dff_insts[port].width,
self.bank.height + max_gap_size_wmask + self.dff.height) self.bank.height + max_gap_size_wmask + self.dff.height)
self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX")
@ -355,11 +355,16 @@ class sram_1bank(sram_base):
""" Connect the output of the data flops to the write driver """ """ Connect the output of the data flops to the write driver """
# This is where the channel will start (y-dimension at least) # This is where the channel will start (y-dimension at least)
for port in self.write_ports: for port in self.write_ports:
if port%2: if self.write_size:
offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch) if port % 2:
offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size + 2)*self.m3_pitch)
else:
offset = self.data_dff_insts[port].ul() + vector(0, 2 * self.m3_pitch)
else: else:
offset = self.data_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) if port%2:
offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch)
else:
offset = self.data_dff_insts[port].ul() + vector(0, 2*self.m1_pitch)
dff_names = ["dout_{}".format(x) for x in range(self.word_size)] dff_names = ["dout_{}".format(x) for x in range(self.word_size)]
dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names]
@ -399,7 +404,7 @@ class sram_1bank(sram_base):
# This is where the channel will start (y-dimension at least) # This is where the channel will start (y-dimension at least)
for port in self.write_ports: for port in self.write_ports:
if port % 2: if port % 2:
offset = self.wmask_dff_insts[port].ll() - vector(0, (self.word_size + 2) * self.m1_pitch) offset = self.wmask_dff_insts[port].ll() - vector(0, (self.num_wmasks+2) * self.m1_pitch)
else: else:
offset = self.wmask_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch) offset = self.wmask_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch)