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Changed routing to allow for 2 write port with write mask.

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This commit is contained in:
jsowash
2019-09-03 14:43:03 -07:00
parent 01bdea23ae
commit dd67490823
4 changed files with 67 additions and 47 deletions
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compiler/modules/write_mask_and_array.py
+17 -5
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@@ -20,7 +20,7 @@ class write_mask_and_array(design.design):
The write mask AND array goes between the write driver array and the sense amp array.
"""
def __init__(self, name, columns, word_size, write_size):
def __init__(self, name, columns, word_size, write_size, port):
design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name))
self.add_comment("columns: {0}".format(columns))
@@ -30,6 +30,7 @@ class write_mask_and_array(design.design):
self.columns = columns
self.word_size = word_size
self.write_size = write_size
self.port = port
self.words_per_row = int(columns / word_size)
self.num_wmasks = int(word_size / write_size)
@@ -106,13 +107,24 @@ class write_mask_and_array(design.design):
self.nand2 = factory.create(module_type="pnand2")
supply_pin=self.nand2.get_pin("vdd")
# Create the enable pin that connects all write mask AND array's B pins
beg_en_pin = self.and2_insts[0].get_pin("B")
end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B")
self.add_layout_pin(text="en",
layer="metal3",
offset=beg_en_pin.bc(),
width = end_en_pin.cx() - beg_en_pin.cx())
if self.port == 0:
self.add_layout_pin(text="en",
layer="metal3",
offset=beg_en_pin.bc(),
width=end_en_pin.cx() - beg_en_pin.cx())
else:
en_to_edge = self.and2.width - beg_en_pin.cx()
self.add_layout_pin(text="en",
layer="metal3",
offset=beg_en_pin.bc(),
width=end_en_pin.cx() - beg_en_pin.cx() + en_to_edge)
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
for i in range(self.num_wmasks):
# Copy remaining layout pins