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OpenRAM
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Some cleanup

This commit is contained in:
mrg 2019-07-05 08:18:58 -07:00
parent 3176ae9d50
commit dd62269e0b
3 changed files with 12 additions and 14 deletions
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2
compiler/debug.py
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@ -85,7 +85,7 @@ def log(str):
# use a static list of strings to store messages until the global paths are set up # use a static list of strings to store messages until the global paths are set up
log.setup_output = [] log.setup_output = []
log.create_file = 1 log.create_file = True
def info(lev, str): def info(lev, str):

18
compiler/modules/port_data.py
View File

@ -16,7 +16,7 @@ from globals import OPTS
class port_data(design.design): class port_data(design.design):
""" """
Create the data port (column mux, sense amps, write driver, etc.) Create the data port (column mux, sense amps, write driver, etc.) for the given port number.
""" """
def __init__(self, sram_config, port, name=""): def __init__(self, sram_config, port, name=""):
@ -25,9 +25,9 @@ class port_data(design.design):
self.port = port self.port = port
if name == "": if name == "":
name = "bank_{0}_{1}".format(self.word_size, self.num_words) name = "port_data_{0}".format(self.port)
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,self.num_words)) debug.info(2, "create data port of size {0} with {1} words per row".format(self.word_size,self.words_per_row))
self.create_netlist() self.create_netlist()
if not OPTS.netlist_only: if not OPTS.netlist_only:
@ -37,7 +37,7 @@ class port_data(design.design):
def create_netlist(self): def create_netlist(self):
self.compute_sizes() self.precompute_constants()
self.add_pins() self.add_pins()
self.add_modules() self.add_modules()
self.create_instances() self.create_instances()
@ -161,7 +161,7 @@ class port_data(design.design):
self.column_mux_array = None self.column_mux_array = None
if self.port in self.write_ports or self.port in self.readwrite_ports: if self.port in self.write_ports:
self.write_driver_array = factory.create(module_type="write_driver_array", self.write_driver_array = factory.create(module_type="write_driver_array",
columns=self.num_cols, columns=self.num_cols,
word_size=self.word_size) word_size=self.word_size)
@ -170,17 +170,15 @@ class port_data(design.design):
self.write_driver_array = None self.write_driver_array = None
def compute_sizes(self): def precompute_constants(self):
""" Computes the required sizes to create the bank """ """ Get some preliminary data ready """
self.num_cols = int(self.words_per_row*self.word_size)
self.num_rows = int(self.num_words / self.words_per_row)
# The central bus is the column address (one hot) and row address (binary) # The central bus is the column address (one hot) and row address (binary)
if self.col_addr_size>0: if self.col_addr_size>0:
self.num_col_addr_lines = 2**self.col_addr_size self.num_col_addr_lines = 2**self.col_addr_size
else: else:
self.num_col_addr_lines = 0 self.num_col_addr_lines = 0
# A space for wells or jogging m2 between modules # A space for wells or jogging m2 between modules
self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"),

6
compiler/sram/sram_config.py
View File

@ -37,7 +37,7 @@ class sram_config:
def compute_sizes(self): def compute_sizes(self):
""" Computes the organization of the memory using bitcell size by trying to make it square.""" """ Computes the organization of the memory using bitcell size by trying to make it square."""
self.bitcell = factory.create(module_type="bitcell") bitcell = factory.create(module_type="bitcell")
debug.check(self.num_banks in [1,2,4], "Valid number of banks are 1 , 2 and 4.") debug.check(self.num_banks in [1,2,4], "Valid number of banks are 1 , 2 and 4.")
@ -48,11 +48,11 @@ class sram_config:
# If this was hard coded, don't dynamically compute it! # If this was hard coded, don't dynamically compute it!
if not self.words_per_row: if not self.words_per_row:
# Compute the area of the bitcells and estimate a square bank (excluding auxiliary circuitry) # Compute the area of the bitcells and estimate a square bank (excluding auxiliary circuitry)
self.bank_area = self.bitcell.width*self.bitcell.height*self.num_bits_per_bank self.bank_area = bitcell.width*bitcell.height*self.num_bits_per_bank
self.bank_side_length = sqrt(self.bank_area) self.bank_side_length = sqrt(self.bank_area)
# Estimate the words per row given the height of the bitcell and the square side length # Estimate the words per row given the height of the bitcell and the square side length
self.tentative_num_cols = int(self.bank_side_length/self.bitcell.width) self.tentative_num_cols = int(self.bank_side_length/bitcell.width)
self.words_per_row = self.estimate_words_per_row(self.tentative_num_cols, self.word_size) self.words_per_row = self.estimate_words_per_row(self.tentative_num_cols, self.word_size)
# Estimate the number of rows given the tentative words per row # Estimate the number of rows given the tentative words per row