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fix pwell pin shape bug

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This commit is contained in:
jcirimel
2021-02-09 20:51:50 -08:00
parent 1c6d4eedd1
commit dbe8a7f1af
6 changed files with 40 additions and 10 deletions
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compiler/base/design.py
+9 -1
View File
@@ -48,7 +48,10 @@ class design(hierarchy_design):
self.add_pin_indices(prop.port_indices)
self.add_pin_names(prop.port_map)
self.add_pin_types(prop.port_types)
def debug_writer(self):
self.gds_write("/home/jesse/output/direct_rw.gds")
(width, height) = utils.get_libcell_size(self.cell_name,
GDS["unit"],
layer[prop.boundary_layer])
@@ -56,7 +59,12 @@ class design(hierarchy_design):
self.pin_map = utils.get_libcell_pins(self.pins,
self.cell_name,
GDS["unit"])
import gdsMill
reader = self.gds
writer = gdsMill.Gds2writer(reader)
writer.writeToFile('/home/jesse/output/direct_rw.gds')
self.gds_write("/home/jesse/output/direct_rw.gds")
self.width = width
self.height = height
compiler/base/utils.py
+9 -6
View File
@@ -148,12 +148,15 @@ def get_gds_pins(pin_names, name, gds_filename, units):
cell[str(pin_name)] = []
pin_list = cell_vlsi.getPinShape(str(pin_name))
for pin_shape in pin_list:
(lpp, boundary) = pin_shape
rect = [vector(boundary[0], boundary[1]),
vector(boundary[2], boundary[3])]
# this is a list because other cells/designs
# may have must-connect pins
cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp))
if pin_shape != None:
(lpp, boundary) = pin_shape
rect = [vector(boundary[0], boundary[1]),
vector(boundary[2], boundary[3])]
# this is a list because other cells/designs
# may have must-connect pins
if isinstance(lpp[1], list):
lpp = (lpp[0], None)
cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp))
_GDS_PINS_CACHE[k] = cell
return dict(cell)