mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed golden values for ngspice delay tests
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afe37e5915
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@ -76,20 +76,21 @@ class timing_sram_test(openram_test):
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'write0_power': [0.1630546],
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'write0_power': [0.1630546],
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'write1_power': [0.1319501]}
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'write1_power': [0.1319501]}
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elif OPTS.tech_name == "scn4m_subm":
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'read1_power': [12.11658],
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golden_data = {'delay_hl': [1.8259260000000002],
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'write1_power': [10.52653],
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'delay_lh': [1.8259260000000002],
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'read0_power': [11.956710000000001],
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'disabled_read0_power': [6.722809],
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'disabled_write0_power': [7.673665],
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'disabled_read1_power': [8.104113],
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'disabled_write1_power': [7.981922000000001],
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'disabled_write0_power': [8.900671],
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'slew_lh': [1.868836],
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'disabled_write1_power': [9.188668],
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'slew_hl': [1.868836],
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'leakage_power': 0.6977637,
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'delay_hl': [1.8598510000000001],
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'min_period': 6.562,
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'delay_lh': [1.8598510000000001],
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'read0_power': [15.45948],
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'leakage_power': 0.005457728,
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'read1_power': [15.48587],
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'disabled_read0_power': [5.904712],
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'slew_hl': [0.1936536],
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'min_period': 6.875,
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'slew_lh': [0.1936536],
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'disabled_read1_power': [7.132159],
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'write0_power': [17.03442],
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'write0_power': [13.406400000000001]}
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'write1_power': [13.05424]}
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else:
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else:
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self.assertTrue(False) # other techs fail
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self.assertTrue(False) # other techs fail
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@ -84,20 +84,21 @@ class timing_sram_test(openram_test):
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'write0_power': [0.44694044],
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'write0_power': [0.44694044],
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'write1_power': [0.36824544000000003]}
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'write1_power': [0.36824544000000003]}
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elif OPTS.tech_name == "scn4m_subm":
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [1.882508],
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golden_data = {'delay_hl': [1.905376],
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'delay_lh': [1.882508],
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'delay_lh': [1.905376],
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'disabled_read0_power': [7.487227],
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'disabled_read0_power': [7.673850999999999],
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'disabled_read1_power': [8.749013],
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'disabled_read1_power': [10.051073],
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'disabled_write0_power': [9.268901],
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'disabled_write0_power': [10.638803],
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'disabled_write1_power': [9.962973],
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'disabled_write1_power': [10.385253],
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'leakage_power': 0.0046686359999999994,
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'leakage_power': 2.704021,
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'min_period': 7.188,
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'min_period': 6.875,
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'read0_power': [16.64011],
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'read0_power': [17.583853],
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'read1_power': [17.20825],
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'read1_power': [17.689162999999997],
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'slew_hl': [2.039655],
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'slew_hl': [0.19331199999999998],
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'slew_lh': [2.039655],
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'slew_lh': [0.19331199999999998],
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'write0_power': [19.31883],
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'write0_power': [20.607043],
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'write1_power': [15.297369999999999]}
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'write1_power': [16.107403]}
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else:
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else:
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self.assertTrue(False) # other techs fail
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self.assertTrue(False) # other techs fail
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@ -12,5 +12,6 @@ num_words = 16
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tech_name = OPTS.tech_name
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tech_name = OPTS.tech_name
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output_name = "sram"
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output_name = "sram"
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analytical_delay = False
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nominal_corner_only = True
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nominal_corner_only = True
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spice_name = "ngspice"
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spice_name = "Xyce"
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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