mirror of https://github.com/VLSIDA/OpenRAM.git
Split graph router class to use it for signal escaping later
This commit is contained in:
Eren Dogan
parent
7be6f2783b
commit
db2a276077
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@ -260,7 +260,7 @@ class sram_1bank(design, verilog, lef):
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elif OPTS.route_supplies == "tree":
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elif OPTS.route_supplies == "tree":
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from openram.router import supply_tree_router as router
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from openram.router import supply_tree_router as router
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else:
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else:
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from openram.router import graph_router as router
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from openram.router import supply_graph_router as router
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rtr=router(layers=self.supply_stack,
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rtr=router(layers=self.supply_stack,
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design=self,
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design=self,
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bbox=bbox,
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bbox=bbox,
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@ -8,4 +8,4 @@ from .signal_escape_router import *
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from .signal_router import *
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from .signal_router import *
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from .supply_grid_router import *
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from .supply_grid_router import *
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from .supply_tree_router import *
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from .supply_tree_router import *
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from .graph_router import *
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from .supply_graph_router import *
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@ -5,25 +5,22 @@
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#
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#
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from openram import debug
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from openram import debug
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from openram.base.vector import vector
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from openram.base.vector import vector
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from openram.base.vector3d import vector3d
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from openram.gdsMill import gdsMill
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from openram.gdsMill import gdsMill
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from openram.tech import GDS
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from openram.tech import GDS
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from openram.tech import drc
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from openram.tech import drc
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from openram.tech import layer as tech_layer
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from openram.tech import layer as tech_layer
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from openram import OPTS
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from openram import OPTS
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from .router_tech import router_tech
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from .router_tech import router_tech
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from .graph import graph
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from .graph_shape import graph_shape
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from .graph_shape import graph_shape
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from .graph_utils import snap
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from .graph_utils import snap
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class graph_router(router_tech):
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class graph_router(router_tech):
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"""
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"""
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This is the router class that uses the Hanan grid method to route pins using
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This is the base class for routers that use the Hanan grid graph method.
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a graph.
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"""
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"""
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def __init__(self, layers, design, bbox=None, pin_type=None):
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def __init__(self, layers, design, bbox=None):
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# `router_tech` contains tech constants for the router
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# `router_tech` contains tech constants for the router
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router_tech.__init__(self, layers, route_track_width=1)
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router_tech.__init__(self, layers, route_track_width=1)
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@ -32,9 +29,6 @@ class graph_router(router_tech):
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self.layers = layers
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self.layers = layers
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# This is the `hierarchy_layout` object
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# This is the `hierarchy_layout` object
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self.design = design
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self.design = design
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# Side supply pin type
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# (can be "top", "bottom", "right", "left", and "ring")
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self.pin_type = pin_type
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# Temporary GDSII file name to find pins and blockages
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# Temporary GDSII file name to find pins and blockages
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self.gds_filename = OPTS.openram_temp + "temp.gds"
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self.gds_filename = OPTS.openram_temp + "temp.gds"
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# Dictionary for vdd and gnd pins
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# Dictionary for vdd and gnd pins
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@ -46,8 +40,6 @@ class graph_router(router_tech):
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self.blockages = []
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self.blockages = []
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# This is all the vias between routing layers
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# This is all the vias between routing layers
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self.vias = []
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self.vias = []
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# New pins are the side supply pins
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self.new_pins = {}
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# Fake pins are imaginary pins on the side supply pins to route other
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# Fake pins are imaginary pins on the side supply pins to route other
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# pins to them
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# pins to them
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self.fake_pins = []
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self.fake_pins = []
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@ -56,81 +48,6 @@ class graph_router(router_tech):
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self.offset = snap(self.track_wire / 2)
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self.offset = snap(self.track_wire / 2)
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def route(self, vdd_name="vdd", gnd_name="gnd"):
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""" Route the given pins in the given order. """
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debug.info(1, "Running router for {} and {}...".format(vdd_name, gnd_name))
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# Save pin names
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self.vdd_name = vdd_name
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self.gnd_name = gnd_name
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# Prepare gdsMill to find pins and blockages
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self.prepare_gds_reader()
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# Find pins to be routed
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self.find_pins(vdd_name)
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self.find_pins(gnd_name)
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# Find blockages and vias
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self.find_blockages()
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self.find_vias()
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# Convert blockages and vias if they overlap a pin
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self.convert_vias()
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self.convert_blockages()
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# Add side pins
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self.calculate_ring_bbox()
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if self.pin_type in ["top", "bottom", "right", "left"]:
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self.add_side_pin(vdd_name)
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self.add_side_pin(gnd_name)
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elif self.pin_type == "ring":
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self.add_ring_pin(vdd_name)
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self.add_ring_pin(gnd_name)
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else:
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debug.warning("Side supply pins aren't created.")
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# Add vdd and gnd pins as blockages as well
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# NOTE: This is done to make vdd and gnd pins DRC-safe
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for pin in self.all_pins:
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self.blockages.append(self.inflate_shape(pin, is_pin=True))
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# Route vdd and gnd
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for pin_name in [vdd_name, gnd_name]:
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pins = self.pins[pin_name]
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# Route closest pins according to the minimum spanning tree
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for source, target in self.get_mst_pairs(list(pins)):
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# This is the routing region scale
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scale = 1
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while True:
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# Create the graph
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g = graph(self)
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region = g.create_graph(source, target, scale)
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# Find the shortest path from source to target
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path = g.find_shortest_path()
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# If there is no path found, exponentially try again with a
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# larger routing region
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if path is None:
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rll, rur = region
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bll, bur = self.ring_bbox
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# Stop scaling the region and throw an error
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if rll.x < bll.x and rll.y < bll.y and \
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rur.x > bur.x and rur.y > bur.y:
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self.write_debug_gds(gds_name="{}error.gds".format(OPTS.openram_temp), g=g, source=source, target=target)
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debug.error("Couldn't route from {} to {}.".format(source, target), -1)
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# Exponentially scale the region
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scale *= 2
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debug.info(0, "Retry routing in larger routing region with scale {}".format(scale))
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continue
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# Create the path shapes on layout
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self.add_path(path)
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# Find the recently added shapes
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self.prepare_gds_reader()
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self.find_blockages(pin_name)
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self.find_vias()
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break
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def prepare_gds_reader(self):
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def prepare_gds_reader(self):
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""" Write the current layout to a temporary file to read the layout. """
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""" Write the current layout to a temporary file to read the layout. """
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@ -299,195 +216,6 @@ class graph_router(router_tech):
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extra_spacing=self.offset)
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extra_spacing=self.offset)
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def calculate_ring_bbox(self, num_vias=3):
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""" Calculate the ring-safe bounding box of the layout. """
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ll, ur = self.design.get_bbox()
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# Calculate the "wideness" of a side supply pin
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wideness = self.track_wire * num_vias + self.track_space * (num_vias - 1)
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# Total wideness is used to find it any pin overlaps in this region. If
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# so, the bbox is shifted to prevent this overlap.
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total_wideness = wideness * 4
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for blockage in self.blockages:
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bll, bur = blockage.rect
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if self.get_zindex(blockage.lpp) == 1: # Vertical
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diff = ll.x + total_wideness - bll.x
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if diff > 0:
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ll = vector(ll.x - diff, ll.y)
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diff = ur.x - total_wideness - bur.x
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if diff < 0:
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ur = vector(ur.x - diff, ur.y)
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else: # Horizontal
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diff = ll.y + total_wideness - bll.y
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if diff > 0:
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ll = vector(ll.x, ll.y - diff)
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diff = ur.y - total_wideness - bur.y
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if diff < 0:
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ur = vector(ur.x, ur.y - diff)
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self.ring_bbox = [ll, ur]
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def add_side_pin(self, pin_name, side, num_vias=3, num_fake_pins=4):
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""" Add supply pin to one side of the layout. """
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ll, ur = self.ring_bbox
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vertical = side in ["left", "right"]
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inner = pin_name == self.gnd_name
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# Calculate wires' wideness
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wideness = self.track_wire * num_vias + self.track_space * (num_vias - 1)
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# Calculate the offset for the inner ring
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if inner:
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margin = wideness * 2
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else:
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margin = 0
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# Calculate the lower left coordinate
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if side == "top":
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offset = vector(ll.x + margin, ur.y - wideness - margin)
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elif side == "bottom":
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offset = vector(ll.x + margin, ll.y + margin)
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elif side == "left":
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offset = vector(ll.x + margin, ll.y + margin)
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elif side == "right":
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offset = vector(ur.x - wideness - margin, ll.y + margin)
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# Calculate width and height
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shape = ur - ll
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if vertical:
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shape_width = wideness
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shape_height = shape.y
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else:
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shape_width = shape.x
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shape_height = wideness
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if inner:
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if vertical:
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shape_height -= margin * 2
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else:
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shape_width -= margin * 2
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# Add this new pin
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layer = self.get_layer(int(vertical))
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pin = self.design.add_layout_pin(text=pin_name,
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layer=layer,
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offset=offset,
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width=shape_width,
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height=shape_height)
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# Add fake pins on this new pin evenly
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fake_pins = []
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if vertical:
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space = (shape_height - (2 * wideness) - num_fake_pins * self.track_wire) / (num_fake_pins + 1)
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start_offset = vector(offset.x, offset.y + wideness)
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else:
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space = (shape_width - (2 * wideness) - num_fake_pins * self.track_wire) / (num_fake_pins + 1)
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start_offset = vector(offset.x + wideness, offset.y)
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for i in range(1, num_fake_pins + 1):
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if vertical:
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offset = vector(start_offset.x, start_offset.y + i * (space + self.track_wire))
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ll = vector(offset.x, offset.y - self.track_wire)
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ur = vector(offset.x + wideness, offset.y)
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else:
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offset = vector(start_offset.x + i * (space + self.track_wire), start_offset.y)
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ll = vector(offset.x - self.track_wire, offset.y)
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ur = vector(offset.x, offset.y + wideness)
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rect = [ll, ur]
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fake_pin = graph_shape(name=pin_name,
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rect=rect,
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layer_name_pp=layer)
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fake_pins.append(fake_pin)
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return pin, fake_pins
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def add_ring_pin(self, pin_name, num_vias=3, num_fake_pins=4):
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""" Add the supply ring to the layout. """
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# Add side pins
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new_pins = []
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for side in ["top", "bottom", "right", "left"]:
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new_shape, fake_pins = self.add_side_pin(pin_name, side, num_vias, num_fake_pins)
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ll, ur = new_shape.rect
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rect = [ll, ur]
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layer = self.get_layer(side in ["left", "right"])
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new_pin = graph_shape(name=pin_name,
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rect=rect,
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layer_name_pp=layer)
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new_pins.append(new_pin)
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self.pins[pin_name].update(fake_pins)
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self.fake_pins.extend(fake_pins)
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# Add vias to the corners
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shift = self.track_wire + self.track_space
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half_wide = self.track_wire / 2
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for i in range(4):
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ll, ur = new_pins[i].rect
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if i % 2:
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top_left = vector(ur.x - (num_vias - 1) * shift - half_wide, ll.y + (num_vias - 1) * shift + half_wide)
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else:
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top_left = vector(ll.x + half_wide, ur.y - half_wide)
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for j in range(num_vias):
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for k in range(num_vias):
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offset = vector(top_left.x + j * shift, top_left.y - k * shift)
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self.design.add_via_center(layers=self.layers,
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offset=offset)
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# Save side pins for routing
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self.new_pins[pin_name] = new_pins
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for pin in new_pins:
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self.blockages.append(self.inflate_shape(pin, is_pin=True))
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def get_mst_pairs(self, pins):
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"""
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Return the pin pairs from the minimum spanning tree in a graph that
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connects all pins together.
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"""
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pin_count = len(pins)
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# Create an adjacency matrix that connects all pins
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edges = [[0] * pin_count for i in range(pin_count)]
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for i in range(pin_count):
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for j in range(pin_count):
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# Skip if they're the same pin
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if i == j:
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continue
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# Skip if both pins are fake
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if pins[i] in self.fake_pins and pins[j] in self.fake_pins:
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continue
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edges[i][j] = pins[i].distance(pins[j])
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pin_connected = [False] * pin_count
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pin_connected[0] = True
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# Add the minimum cost edge in each iteration (Prim's)
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mst_pairs = []
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for i in range(pin_count - 1):
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min_cost = float("inf")
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s = 0
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t = 0
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# Iterate over already connected pins
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for m in range(pin_count):
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# Skip if not connected
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if not pin_connected[m]:
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continue
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# Iterate over this pin's neighbors
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for n in range(pin_count):
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# Skip if already connected or isn't a neighbor
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if pin_connected[n] or edges[m][n] == 0:
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continue
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# Choose this edge if it's better the the current one
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if edges[m][n] < min_cost:
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min_cost = edges[m][n]
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s = m
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t = n
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pin_connected[t] = True
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mst_pairs.append((pins[s], pins[t]))
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return mst_pairs
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def add_path(self, path):
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def add_path(self, path):
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""" Add the route path to the layout. """
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""" Add the route path to the layout. """
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@ -546,12 +274,6 @@ class graph_router(router_tech):
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height=abs(diff.y) + self.track_wire)
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height=abs(diff.y) + self.track_wire)
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def get_new_pins(self, name):
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""" Return the new supply pins added by this router. """
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||||||
return self.new_pins[name]
|
|
||||||
|
|
||||||
|
|
||||||
def write_debug_gds(self, gds_name="debug_route.gds", g=None, source=None, target=None):
|
def write_debug_gds(self, gds_name="debug_route.gds", g=None, source=None, target=None):
|
||||||
""" Write the debug GDSII file for the router. """
|
""" Write the debug GDSII file for the router. """
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,298 @@
|
||||||
|
# See LICENSE for licensing information.
|
||||||
|
#
|
||||||
|
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
|
||||||
|
# All rights reserved.
|
||||||
|
#
|
||||||
|
from openram import debug
|
||||||
|
from openram.base.vector import vector
|
||||||
|
from openram import OPTS
|
||||||
|
from .graph import graph
|
||||||
|
from .graph_router import graph_router
|
||||||
|
from .graph_shape import graph_shape
|
||||||
|
|
||||||
|
|
||||||
|
class supply_graph_router(graph_router):
|
||||||
|
"""
|
||||||
|
This is the supply router that uses the Hanan grid graph method.
|
||||||
|
"""
|
||||||
|
|
||||||
|
def __init__(self, layers, design, bbox=None, pin_type=None):
|
||||||
|
|
||||||
|
# `router_tech` contains tech constants for the router
|
||||||
|
graph_router.__init__(self, layers, design, bbox)
|
||||||
|
|
||||||
|
# Side supply pin type
|
||||||
|
# (can be "top", "bottom", "right", "left", and "ring")
|
||||||
|
self.pin_type = pin_type
|
||||||
|
# New pins are the side supply pins
|
||||||
|
self.new_pins = {}
|
||||||
|
|
||||||
|
|
||||||
|
def route(self, vdd_name="vdd", gnd_name="gnd"):
|
||||||
|
""" Route the given pins in the given order. """
|
||||||
|
debug.info(1, "Running router for {} and {}...".format(vdd_name, gnd_name))
|
||||||
|
|
||||||
|
# Save pin names
|
||||||
|
self.vdd_name = vdd_name
|
||||||
|
self.gnd_name = gnd_name
|
||||||
|
|
||||||
|
# Prepare gdsMill to find pins and blockages
|
||||||
|
self.prepare_gds_reader()
|
||||||
|
|
||||||
|
# Find pins to be routed
|
||||||
|
self.find_pins(vdd_name)
|
||||||
|
self.find_pins(gnd_name)
|
||||||
|
|
||||||
|
# Find blockages and vias
|
||||||
|
self.find_blockages()
|
||||||
|
self.find_vias()
|
||||||
|
|
||||||
|
# Convert blockages and vias if they overlap a pin
|
||||||
|
self.convert_vias()
|
||||||
|
self.convert_blockages()
|
||||||
|
|
||||||
|
# Add side pins
|
||||||
|
self.calculate_ring_bbox()
|
||||||
|
if self.pin_type in ["top", "bottom", "right", "left"]:
|
||||||
|
self.add_side_pin(vdd_name)
|
||||||
|
self.add_side_pin(gnd_name)
|
||||||
|
elif self.pin_type == "ring":
|
||||||
|
self.add_ring_pin(vdd_name)
|
||||||
|
self.add_ring_pin(gnd_name)
|
||||||
|
else:
|
||||||
|
debug.warning("Side supply pins aren't created.")
|
||||||
|
|
||||||
|
# Add vdd and gnd pins as blockages as well
|
||||||
|
# NOTE: This is done to make vdd and gnd pins DRC-safe
|
||||||
|
for pin in self.all_pins:
|
||||||
|
self.blockages.append(self.inflate_shape(pin, is_pin=True))
|
||||||
|
|
||||||
|
# Route vdd and gnd
|
||||||
|
for pin_name in [vdd_name, gnd_name]:
|
||||||
|
pins = self.pins[pin_name]
|
||||||
|
# Route closest pins according to the minimum spanning tree
|
||||||
|
for source, target in self.get_mst_pairs(list(pins)):
|
||||||
|
# This is the routing region scale
|
||||||
|
scale = 1
|
||||||
|
while True:
|
||||||
|
# Create the graph
|
||||||
|
g = graph(self)
|
||||||
|
region = g.create_graph(source, target, scale)
|
||||||
|
# Find the shortest path from source to target
|
||||||
|
path = g.find_shortest_path()
|
||||||
|
# If there is no path found, exponentially try again with a
|
||||||
|
# larger routing region
|
||||||
|
if path is None:
|
||||||
|
rll, rur = region
|
||||||
|
bll, bur = self.ring_bbox
|
||||||
|
# Stop scaling the region and throw an error
|
||||||
|
if rll.x < bll.x and rll.y < bll.y and \
|
||||||
|
rur.x > bur.x and rur.y > bur.y:
|
||||||
|
self.write_debug_gds(gds_name="{}error.gds".format(OPTS.openram_temp), g=g, source=source, target=target)
|
||||||
|
debug.error("Couldn't route from {} to {}.".format(source, target), -1)
|
||||||
|
# Exponentially scale the region
|
||||||
|
scale *= 2
|
||||||
|
debug.info(0, "Retry routing in larger routing region with scale {}".format(scale))
|
||||||
|
continue
|
||||||
|
# Create the path shapes on layout
|
||||||
|
self.add_path(path)
|
||||||
|
# Find the recently added shapes
|
||||||
|
self.prepare_gds_reader()
|
||||||
|
self.find_blockages(pin_name)
|
||||||
|
self.find_vias()
|
||||||
|
break
|
||||||
|
|
||||||
|
|
||||||
|
def calculate_ring_bbox(self, num_vias=3):
|
||||||
|
""" Calculate the ring-safe bounding box of the layout. """
|
||||||
|
|
||||||
|
ll, ur = self.design.get_bbox()
|
||||||
|
# Calculate the "wideness" of a side supply pin
|
||||||
|
wideness = self.track_wire * num_vias + self.track_space * (num_vias - 1)
|
||||||
|
# Total wideness is used to find it any pin overlaps in this region. If
|
||||||
|
# so, the bbox is shifted to prevent this overlap.
|
||||||
|
total_wideness = wideness * 4
|
||||||
|
for blockage in self.blockages:
|
||||||
|
bll, bur = blockage.rect
|
||||||
|
if self.get_zindex(blockage.lpp) == 1: # Vertical
|
||||||
|
diff = ll.x + total_wideness - bll.x
|
||||||
|
if diff > 0:
|
||||||
|
ll = vector(ll.x - diff, ll.y)
|
||||||
|
diff = ur.x - total_wideness - bur.x
|
||||||
|
if diff < 0:
|
||||||
|
ur = vector(ur.x - diff, ur.y)
|
||||||
|
else: # Horizontal
|
||||||
|
diff = ll.y + total_wideness - bll.y
|
||||||
|
if diff > 0:
|
||||||
|
ll = vector(ll.x, ll.y - diff)
|
||||||
|
diff = ur.y - total_wideness - bur.y
|
||||||
|
if diff < 0:
|
||||||
|
ur = vector(ur.x, ur.y - diff)
|
||||||
|
self.ring_bbox = [ll, ur]
|
||||||
|
|
||||||
|
|
||||||
|
def add_side_pin(self, pin_name, side, num_vias=3, num_fake_pins=4):
|
||||||
|
""" Add supply pin to one side of the layout. """
|
||||||
|
|
||||||
|
ll, ur = self.ring_bbox
|
||||||
|
vertical = side in ["left", "right"]
|
||||||
|
inner = pin_name == self.gnd_name
|
||||||
|
|
||||||
|
# Calculate wires' wideness
|
||||||
|
wideness = self.track_wire * num_vias + self.track_space * (num_vias - 1)
|
||||||
|
|
||||||
|
# Calculate the offset for the inner ring
|
||||||
|
if inner:
|
||||||
|
margin = wideness * 2
|
||||||
|
else:
|
||||||
|
margin = 0
|
||||||
|
|
||||||
|
# Calculate the lower left coordinate
|
||||||
|
if side == "top":
|
||||||
|
offset = vector(ll.x + margin, ur.y - wideness - margin)
|
||||||
|
elif side == "bottom":
|
||||||
|
offset = vector(ll.x + margin, ll.y + margin)
|
||||||
|
elif side == "left":
|
||||||
|
offset = vector(ll.x + margin, ll.y + margin)
|
||||||
|
elif side == "right":
|
||||||
|
offset = vector(ur.x - wideness - margin, ll.y + margin)
|
||||||
|
|
||||||
|
# Calculate width and height
|
||||||
|
shape = ur - ll
|
||||||
|
if vertical:
|
||||||
|
shape_width = wideness
|
||||||
|
shape_height = shape.y
|
||||||
|
else:
|
||||||
|
shape_width = shape.x
|
||||||
|
shape_height = wideness
|
||||||
|
if inner:
|
||||||
|
if vertical:
|
||||||
|
shape_height -= margin * 2
|
||||||
|
else:
|
||||||
|
shape_width -= margin * 2
|
||||||
|
|
||||||
|
# Add this new pin
|
||||||
|
layer = self.get_layer(int(vertical))
|
||||||
|
pin = self.design.add_layout_pin(text=pin_name,
|
||||||
|
layer=layer,
|
||||||
|
offset=offset,
|
||||||
|
width=shape_width,
|
||||||
|
height=shape_height)
|
||||||
|
|
||||||
|
# Add fake pins on this new pin evenly
|
||||||
|
fake_pins = []
|
||||||
|
if vertical:
|
||||||
|
space = (shape_height - (2 * wideness) - num_fake_pins * self.track_wire) / (num_fake_pins + 1)
|
||||||
|
start_offset = vector(offset.x, offset.y + wideness)
|
||||||
|
else:
|
||||||
|
space = (shape_width - (2 * wideness) - num_fake_pins * self.track_wire) / (num_fake_pins + 1)
|
||||||
|
start_offset = vector(offset.x + wideness, offset.y)
|
||||||
|
for i in range(1, num_fake_pins + 1):
|
||||||
|
if vertical:
|
||||||
|
offset = vector(start_offset.x, start_offset.y + i * (space + self.track_wire))
|
||||||
|
ll = vector(offset.x, offset.y - self.track_wire)
|
||||||
|
ur = vector(offset.x + wideness, offset.y)
|
||||||
|
else:
|
||||||
|
offset = vector(start_offset.x + i * (space + self.track_wire), start_offset.y)
|
||||||
|
ll = vector(offset.x - self.track_wire, offset.y)
|
||||||
|
ur = vector(offset.x, offset.y + wideness)
|
||||||
|
rect = [ll, ur]
|
||||||
|
fake_pin = graph_shape(name=pin_name,
|
||||||
|
rect=rect,
|
||||||
|
layer_name_pp=layer)
|
||||||
|
fake_pins.append(fake_pin)
|
||||||
|
return pin, fake_pins
|
||||||
|
|
||||||
|
|
||||||
|
def add_ring_pin(self, pin_name, num_vias=3, num_fake_pins=4):
|
||||||
|
""" Add the supply ring to the layout. """
|
||||||
|
|
||||||
|
# Add side pins
|
||||||
|
new_pins = []
|
||||||
|
for side in ["top", "bottom", "right", "left"]:
|
||||||
|
new_shape, fake_pins = self.add_side_pin(pin_name, side, num_vias, num_fake_pins)
|
||||||
|
ll, ur = new_shape.rect
|
||||||
|
rect = [ll, ur]
|
||||||
|
layer = self.get_layer(side in ["left", "right"])
|
||||||
|
new_pin = graph_shape(name=pin_name,
|
||||||
|
rect=rect,
|
||||||
|
layer_name_pp=layer)
|
||||||
|
new_pins.append(new_pin)
|
||||||
|
self.pins[pin_name].update(fake_pins)
|
||||||
|
self.fake_pins.extend(fake_pins)
|
||||||
|
|
||||||
|
# Add vias to the corners
|
||||||
|
shift = self.track_wire + self.track_space
|
||||||
|
half_wide = self.track_wire / 2
|
||||||
|
for i in range(4):
|
||||||
|
ll, ur = new_pins[i].rect
|
||||||
|
if i % 2:
|
||||||
|
top_left = vector(ur.x - (num_vias - 1) * shift - half_wide, ll.y + (num_vias - 1) * shift + half_wide)
|
||||||
|
else:
|
||||||
|
top_left = vector(ll.x + half_wide, ur.y - half_wide)
|
||||||
|
for j in range(num_vias):
|
||||||
|
for k in range(num_vias):
|
||||||
|
offset = vector(top_left.x + j * shift, top_left.y - k * shift)
|
||||||
|
self.design.add_via_center(layers=self.layers,
|
||||||
|
offset=offset)
|
||||||
|
|
||||||
|
# Save side pins for routing
|
||||||
|
self.new_pins[pin_name] = new_pins
|
||||||
|
for pin in new_pins:
|
||||||
|
self.blockages.append(self.inflate_shape(pin, is_pin=True))
|
||||||
|
|
||||||
|
|
||||||
|
def get_mst_pairs(self, pins):
|
||||||
|
"""
|
||||||
|
Return the pin pairs from the minimum spanning tree in a graph that
|
||||||
|
connects all pins together.
|
||||||
|
"""
|
||||||
|
|
||||||
|
pin_count = len(pins)
|
||||||
|
|
||||||
|
# Create an adjacency matrix that connects all pins
|
||||||
|
edges = [[0] * pin_count for i in range(pin_count)]
|
||||||
|
for i in range(pin_count):
|
||||||
|
for j in range(pin_count):
|
||||||
|
# Skip if they're the same pin
|
||||||
|
if i == j:
|
||||||
|
continue
|
||||||
|
# Skip if both pins are fake
|
||||||
|
if pins[i] in self.fake_pins and pins[j] in self.fake_pins:
|
||||||
|
continue
|
||||||
|
edges[i][j] = pins[i].distance(pins[j])
|
||||||
|
|
||||||
|
pin_connected = [False] * pin_count
|
||||||
|
pin_connected[0] = True
|
||||||
|
|
||||||
|
# Add the minimum cost edge in each iteration (Prim's)
|
||||||
|
mst_pairs = []
|
||||||
|
for i in range(pin_count - 1):
|
||||||
|
min_cost = float("inf")
|
||||||
|
s = 0
|
||||||
|
t = 0
|
||||||
|
# Iterate over already connected pins
|
||||||
|
for m in range(pin_count):
|
||||||
|
# Skip if not connected
|
||||||
|
if not pin_connected[m]:
|
||||||
|
continue
|
||||||
|
# Iterate over this pin's neighbors
|
||||||
|
for n in range(pin_count):
|
||||||
|
# Skip if already connected or isn't a neighbor
|
||||||
|
if pin_connected[n] or edges[m][n] == 0:
|
||||||
|
continue
|
||||||
|
# Choose this edge if it's better the the current one
|
||||||
|
if edges[m][n] < min_cost:
|
||||||
|
min_cost = edges[m][n]
|
||||||
|
s = m
|
||||||
|
t = n
|
||||||
|
pin_connected[t] = True
|
||||||
|
mst_pairs.append((pins[s], pins[t]))
|
||||||
|
|
||||||
|
return mst_pairs
|
||||||
|
|
||||||
|
|
||||||
|
def get_new_pins(self, name):
|
||||||
|
""" Return the new supply pins added by this router. """
|
||||||
|
|
||||||
|
return self.new_pins[name]
|
||||||
Loading…
Reference in New Issue