Split graph router class to use it for signal escaping later

2026-08-29 01:24:39 +02:00 · 2023-07-31 19:43:09 -07:00
parent 7be6f2783b
commit db2a276077
4 changed files with 302 additions and 282 deletions
@@ -260,7 +260,7 @@ class sram_1bank(design, verilog, lef):
        elif OPTS.route_supplies == "tree":
            from openram.router import supply_tree_router as router
        else:
-            from openram.router import graph_router as router
+            from openram.router import supply_graph_router as router
        rtr=router(layers=self.supply_stack,
                   design=self,
                   bbox=bbox,