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Changed input format for delay module in xyce delay test.

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This commit is contained in:
Hunter Nichols
2021-05-26 20:11:30 -07:00
parent b3bcf48d2e
commit da67edbde8
1 changed files with 5 additions and 1 deletions
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compiler/tests/21_xyce_delay_test.py
+5 -1
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@@ -51,7 +51,11 @@ class timing_sram_test(openram_test):
import tech
loads = [tech.spice["dff_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
load_slews = []
for slew in slews:
for load in loads:
load_slews.append((load, slew))
data, port_data = d.analyze(probe_address, probe_data, load_slews)
# Combine info about port into all data
data.update(port_data[0])