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capped norbl scmos passing

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Jesse Cirimelli-Low
2023-07-30 22:39:23 -07:00
parent 6b12d442fa
commit d9d8cb2983
2 changed files with 14 additions and 14 deletions
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compiler/modules/bitcell_array.py
+9 -4
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@@ -62,12 +62,17 @@ class bitcell_array(bitcell_base_array):
self.cell_inst={}
core_block = [[0 for x in range(2)] for y in range(2)]
# block[col][row
core_block[0][0] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True)
core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True, mirror='MX')
core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, is_bitcell=True, mirror='MY')
core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, is_bitcell=True, mirror='XY')
core_block[(0 + self.column_offset) %2][0] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True)
core_block[(0 + self.column_offset) %2][1] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True, mirror='MX')
core_block[(1 + self.column_offset) %2][0] = geometry.instance("core_0_1", mod=self.cell, is_bitcell=True, mirror='MY')
core_block[(1 + self.column_offset) %2][1] = geometry.instance("core_1_1", mod=self.cell, is_bitcell=True, mirror='XY')
self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
self.pattern.connect_array()
for key in self.cell_inst.keys():
if key != (0,0):
self.trim_insts.add(self.cell_inst[key].name)
def analytical_power(self, corner, load):
"""Power of Bitcell array and bitline in nW."""