Lots of PEP8 cleanup. Refactor path graph to simulation class.

compiler/modules/bank.py

@@ -1076,14 +1076,30 @@ class bank(design.design):
                             offset=control_pos)
 
     def graph_exclude_precharge(self):
-        """Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
+        """
+        Precharge adds a loop between bitlines, can be excluded to reduce complexity
+        """
         for port in self.read_ports:
             if self.port_data[port]:
                 self.port_data[port].graph_exclude_precharge()
                 
     def get_cell_name(self, inst_name, row, col):
-        """Gets the spice name of the target bitcell."""
+        """
+        Gets the spice name of the target bitcell.
+        """
         return self.bitcell_array_inst.mod.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name,
                                                          row,
                                                          col)
 
+    def graph_exclude_bits(self, targ_row, targ_col):
+        """
+        Excludes bits in column from being added to graph except target
+        """
+        self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
+
+    def clear_exclude_bits(self):
+        """ 
+        Clears the bit exclusions
+        """
+        self.bitcell_array.clear_exclude_bits()
+        

compiler/modules/bitcell_array.py

@@ -105,7 +105,9 @@ class bitcell_array(bitcell_base_array):
         return bl_wire
 
     def graph_exclude_bits(self, targ_row, targ_col):
-        """Excludes bits in column from being added to graph except target"""
+        """
+        Excludes bits in column from being added to graph except target
+        """
         # Function is not robust with column mux configurations
         for row in range(self.row_size):
             for col in range(self.column_size):

compiler/modules/global_bitcell_array.py

@@ -297,6 +297,15 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
         for i, local_col in enumerate(self.col_offsets):
             if local_col > col:
                 break
+        else:
+            # In this case, we it should be in the last bitcell array
+            i = len(self.col_offsets)
             
         return self.local_mods[i - 1].get_cell_name(inst_name + '.x' + self.local_insts[i - 1].name, row, col)
             
+    def clear_exclude_bits(self):
+        """ 
+        Clears the bit exclusions
+        """
+        for mod in self.local_mods:
+            mod.clear_exclude_bits()

compiler/modules/local_bitcell_array.py

@@ -279,4 +279,10 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
     def get_cell_name(self, inst_name, row, col):
         """Gets the spice name of the target bitcell."""
         return self.bitcell_array.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, row, col)
-        
+
+    def clear_exclude_bits(self):
+        """ 
+        Clears the bit exclusions
+        """
+        self.bitcell_array.clear_exclude_bits()
+    

compiler/modules/replica_bitcell_array.py

@@ -529,15 +529,27 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
         return bl_wire
 
     def graph_exclude_bits(self, targ_row, targ_col):
-        """Excludes bits in column from being added to graph except target"""
+        """
+        Excludes bits in column from being added to graph except target
+        """
         self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
 
     def graph_exclude_replica_col_bits(self):
-        """Exclude all replica/dummy cells in the replica columns except the replica bit."""
+        """
+        Exclude all replica/dummy cells in the replica columns except the replica bit.
+        """
 
         for port in self.left_rbl + self.right_rbl:
             self.replica_columns[port].exclude_all_but_replica()
 
     def get_cell_name(self, inst_name, row, col):
-        """Gets the spice name of the target bitcell."""
+        """
+        Gets the spice name of the target bitcell.
+        """
         return self.bitcell_array.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, row, col)
+
+    def clear_exclude_bits(self):
+        """ 
+        Clears the bit exclusions
+        """
+        self.bitcell_array.init_graph_params()

compiler/modules/replica_column.py

@@ -200,8 +200,10 @@ class replica_column(bitcell_base_array):
             return self.bitline_names[port]
 
     def get_bitcell_pins(self, row, col):
-        """ Creates a list of connections in the bitcell,
-        indexed by column and row, for instance use in bitcell_array """
+        """ 
+        Creates a list of connections in the bitcell,
+        indexed by column and row, for instance use in bitcell_array 
+        """
         bitcell_pins = []
         for port in self.all_ports:
             bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
@@ -212,8 +214,10 @@ class replica_column(bitcell_base_array):
         return bitcell_pins
 
     def get_bitcell_pins_col_cap(self, row, col):
-        """ Creates a list of connections in the bitcell,
-        indexed by column and row, for instance use in bitcell_array """
+        """ 
+        Creates a list of connections in the bitcell,
+        indexed by column and row, for instance use in bitcell_array
+        """
         bitcell_pins = []
         for port in self.all_ports:
             bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
@@ -223,7 +227,9 @@ class replica_column(bitcell_base_array):
         return bitcell_pins
 
     def exclude_all_but_replica(self):
-        """Excludes all bits except the replica cell (self.replica_bit)."""
+        """
+        Excludes all bits except the replica cell (self.replica_bit).
+        """
 
         for row, cell in self.cell_inst.items():
             if row != self.replica_bit: